1. 20 Jan, 2016 2 commits
  2. 15 Jan, 2016 10 commits
    • Simon Horman's avatar
      PCI: Limit config space size for Netronome NFP4000 · c2e771b0
      Simon Horman authored
      Like the NFP6000, the NFP4000 as an erratum where reading/writing to PCI
      config space addresses above 0x600 can cause the NFP to generate PCIe
      completion timeouts.
      
      Limit the NFP4000's PF's config space size to 0x600 bytes as is already
      done for the NFP6000.
      
      The NFP4000's VF is 0x6004 (PCI_DEVICE_ID_NETRONOME_NFP6000_VF), the same
      device ID as the NFP6000's VF.  Thus, its config space is already limited
      by the existing use of quirk_nfp6000().
      Signed-off-by: default avatarSimon Horman <simon.horman@netronome.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      c2e771b0
    • Simon Horman's avatar
      PCI: Add Netronome NFP4000 PF device ID · 69874ec2
      Simon Horman authored
      Add the device ID for the PF of the NFP4000.  The device ID for the VF,
      0x6003, is already present as PCI_DEVICE_ID_NETRONOME_NFP6000_VF.
      Signed-off-by: default avatarSimon Horman <simon.horman@netronome.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      69874ec2
    • Bjorn Helgaas's avatar
      Merge branch 'pci/host-vmd' into next · 3a6384ba
      Bjorn Helgaas authored
      * pci/host-vmd:
        x86/PCI: Add driver for Intel Volume Management Device (VMD)
        PCI/AER: Use 32 bit PCI domain numbers
        x86/PCI: Allow DMA ops specific to a PCI domain
        irqdomain: Export irq_domain_set_info() for module use
        genirq/MSI: Relax msi_domain_alloc() to support parentless MSI irqdomains
      3a6384ba
    • Keith Busch's avatar
      x86/PCI: Add driver for Intel Volume Management Device (VMD) · 185a383a
      Keith Busch authored
      The Intel Volume Management Device (VMD) is a Root Complex Integrated
      Endpoint that acts as a host bridge to a secondary PCIe domain.  BIOS can
      reassign one or more Root Ports to appear within a VMD domain instead of
      the primary domain.  The immediate benefit is that additional PCIe domains
      allow more than 256 buses in a system by letting bus numbers be reused
      across different domains.
      
      VMD domains do not define ACPI _SEG, so to avoid domain clashing with host
      bridges defining this segment, VMD domains start at 0x10000, which is
      greater than the highest possible 16-bit ACPI defined _SEG.
      
      This driver enumerates and enables the domain using the root bus
      configuration interface provided by the PCI subsystem.  The driver provides
      configuration space accessor functions (pci_ops), bus and memory resources,
      an MSI IRQ domain with irq_chip implementation, and DMA operations
      necessary to use devices through the VMD endpoint's interface.
      
      VMD routes I/O as follows:
      
         1) Configuration Space: BAR 0 ("CFGBAR") of VMD provides the base
         address and size for configuration space register access to VMD-owned
         root ports.  It works similarly to MMCONFIG for extended configuration
         space.  Bus numbering is independent and does not conflict with the
         primary domain.
      
         2) MMIO Space: BARs 2 and 4 ("MEMBAR1" and "MEMBAR2") of VMD provide the
         base address, size, and type for MMIO register access.  These addresses
         are not translated by VMD hardware; they are simply reservations to be
         distributed to root ports' memory base/limit registers and subdivided
         among devices downstream.
      
         3) DMA: To interact appropriately with an IOMMU, the source ID DMA read
         and write requests are translated to the bus-device-function of the VMD
         endpoint.  Otherwise, DMA operates normally without VMD-specific address
         translation.
      
         4) Interrupts: Part of VMD's BAR 4 is reserved for VMD's MSI-X Table and
         PBA.  MSIs from VMD domain devices and ports are remapped to appear as
         if they were issued using one of VMD's MSI-X table entries.  Each MSI
         and MSI-X address of VMD-owned devices and ports has a special format
         where the address refers to specific entries in the VMD's MSI-X table.
         As with DMA, the interrupt source ID is translated to VMD's
         bus-device-function.
      
         The driver provides its own MSI and MSI-X configuration functions
         specific to how MSI messages are used within the VMD domain, and
         provides an irq_chip for independent IRQ allocation to relay interrupts
         from VMD's interrupt handler to the appropriate device driver's handler.
      
         5) Errors: PCIe error message are intercepted by the root ports normally
         (e.g., AER), except with VMD, system errors (i.e., firmware first) are
         disabled by default.  AER and hotplug interrupts are translated in the
         same way as endpoint interrupts.
      
         6) VMD does not support INTx interrupts or IO ports.  Devices or drivers
         requiring these features should either not be placed below VMD-owned
         root ports, or VMD should be disabled by BIOS for such endpoints.
      
      [bhelgaas: add VMD BAR #defines, factor out vmd_cfg_addr(), rework VMD
      resource setup, whitespace, changelog]
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Acked-by: Thomas Gleixner <tglx@linutronix.de> (IRQ-related parts)
      185a383a
    • Keith Busch's avatar
      PCI/AER: Use 32 bit PCI domain numbers · 28ef241f
      Keith Busch authored
      The Intel Volume Management Device (VMD) supports 32-bit domain numbers.
      To accommodate this, use u32 instead of u16 to store domain numbers.
      
      [bhelgaas: changelog]
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      28ef241f
    • Keith Busch's avatar
      x86/PCI: Allow DMA ops specific to a PCI domain · d9c3d6ff
      Keith Busch authored
      The Intel Volume Management Device (VMD) is a PCIe endpoint that acts as a
      host bridge to another PCI domain.  When devices below the VMD perform DMA,
      the VMD replaces their DMA source IDs with its own source ID.  Therefore,
      those devices require special DMA ops.
      
      Add interfaces to allow the VMD driver to set up dma_ops for the devices
      below it.
      
      [bhelgaas: remove "extern", add "static", changelog]
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      d9c3d6ff
    • Keith Busch's avatar
      irqdomain: Export irq_domain_set_info() for module use · 64bce3e8
      Keith Busch authored
      Export irq_domain_set_info() for module use.  It will be used by the Volume
      Management Device driver.
      
      [bhelgaas: changelog]
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
      64bce3e8
    • Bjorn Helgaas's avatar
      Merge branches 'pci/hotplug' and 'pci/resource' into next · 47235841
      Bjorn Helgaas authored
      * pci/hotplug:
        PCI: ibmphp: Remove unneeded NULL test
        PCI: hotplug: Use list_for_each_entry() to simplify code
        PCI: acpiphp_ibm: Fix null dereferences on null ibm_slot
      
      * pci/resource:
        PCI: Avoid iterating through memory outside the resource window
        PCI: Fix minimum allocation address overwrite
      47235841
    • Bjorn Helgaas's avatar
      Merge branches 'pci/host', 'pci/host-designware', 'pci/host-hisi',... · c111e8bf
      Bjorn Helgaas authored
      Merge branches 'pci/host', 'pci/host-designware', 'pci/host-hisi', 'pci/host-qcom' and 'pci/host-rcar' into next
      
      * pci/host:
        PCI: host: Add of_pci_get_host_bridge_resources() stub
        PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD
      
      * pci/host-designware:
        PCI: designware: Make config accessor override checking symmetric
        PCI: designware: Simplify control flow
      
      * pci/host-hisi:
        PCI: hisi: Add support for HiSilicon Hip06 PCIe host controllers
      
      * pci/host-qcom:
        ARM: dts: ifc6410: enable PCIe DT node for this board
        ARM: dts: apq8064: add PCIe devicetree node
        PCI: qcom: Add Qualcomm PCIe controller driver
        PCI: qcom: Document PCIe devicetree bindings
        PCI: designware: Ensure ATU is enabled before IO/conf space accesses
      
      * pci/host-rcar:
        PCI: rcar: Add Gen2 PHY setup to pcie-rcar
        PCI: rcar: Add runtime PM support to pcie-rcar
        PCI: rcar: Remove unused pci_sys_data struct from pcie-rcar
      c111e8bf
    • Arnd Bergmann's avatar
      PCI: host: Add of_pci_get_host_bridge_resources() stub · 40704b12
      Arnd Bergmann authored
      The pcie-rcar driver can be built for any ARM platform (for COMPILE_TEST)
      including those without CONFIG_OF enabled, and that results in a
      compile-time error:
      
        drivers/pci/host/pcie-rcar.c: In function 'rcar_pcie_parse_request_of_pci_ranges':
        drivers/pci/host/pcie-rcar.c:939:8: error: implicit declaration of function 'of_pci_get_host_bridge_resources' [-Werror=implicit-function-declaration]
          err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, &iobase);
      
      Add a of_pci_get_host_bridge_resources() stub function defined when
      CONFIG_OF_ADDRESS is disabled to allow compile-testing on all platforms.
      This mirrors what we do for other OF-specific functions.
      
      Fixes: 5d2917d4 ("PCI: rcar: Convert to DT resource parsing API")
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Acked-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
      Acked-by: default avatarSimon Horman <horms+renesas@verge.net.au>
      40704b12
  3. 14 Jan, 2016 1 commit
  4. 11 Jan, 2016 6 commits
  5. 10 Jan, 2016 1 commit
  6. 08 Jan, 2016 4 commits
  7. 07 Jan, 2016 2 commits
    • Bjorn Helgaas's avatar
      Merge branches 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc' and 'pci/host-rcar' into next · 65d5b109
      Bjorn Helgaas authored
      * pci/host-generic:
        PCI: generic,versatile: Remove unused pci_sys_data structures
      
      * pci/host-imx6:
        PCI: imx6: Add support for active-low reset GPIO
        PCI: imx6: Use gpio_set_value_cansleep()
      
      * pci/host-iproc:
        PCI: iproc: Add iProc PCIe MSI support
        PCI: iproc: Add iProc PCIe MSI device tree binding
        PCI: iproc: Add PAXC interface support
        PCI: iproc: Update iProc PCIe device tree binding
        PCI: iproc: Do not use 0x in front of %pap
        PCI: iproc: Hide CONFIG_PCIE_IPROC
      
      * pci/host-rcar:
        PCI: rcar: Add gen2 fallback compatibility string for pcie-rcar
        PCI: rcar: Add gen2 fallback compatibility string for pci-rcar-gen2
        PCI: rcar: Add support for R-Car H3 to pcie-rcar
        Revert "PCI: rcar: Build pcie-rcar.c only on ARM"
        PCI: rcar: Convert to DT resource parsing API
        PCI: rcar: Allow DT to override default window settings
      65d5b109
    • Ray Jui's avatar
      PCI: iproc: Add iProc PCIe MSI support · 3bc2b234
      Ray Jui authored
      Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based
      platforms.
      
      The iProc PCIe MSI support deploys an event queue-based implementation.
      Each event queue is serviced by a GIC interrupt and can support up to 64
      MSI vectors.  Host memory is allocated for the event queues, and each event
      queue consists of 64 word-sized entries.  MSI data is written to the lower
      16-bit of each entry, whereas the upper 16-bit of the entry is reserved for
      the controller for internal processing.
      
      Each event queue is tracked by a head pointer and tail pointer.  Head
      pointer indicates the next entry in the event queue to be processed by
      the driver and is updated by the driver after processing is done.
      The controller uses the tail pointer as the next MSI data insertion
      point.  The controller ensures MSI data is flushed to host memory before
      updating the tail pointer and then triggering the interrupt.
      
      MSI IRQ affinity is supported by evenly distributing the interrupts to each
      CPU core.  MSI vector is moved from one GIC interrupt to another in order
      to steer to the target CPU.
      
      Therefore, the actual number of supported MSI vectors is:
      
        M * 64 / N
      
      where M denotes the number of GIC interrupts (event queues), and N denotes
      the number of CPU cores.
      
      This iProc event queue-based MSI support should not be used with newer
      platforms with integrated MSI support in the GIC (e.g., giv2m or
      gicv3-its).
      
      [bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>]
      Signed-off-by: default avatarRay Jui <rjui@broadcom.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarAnup Patel <anup.patel@broadcom.com>
      Reviewed-by: default avatarVikram Prakash <vikramp@broadcom.com>
      Reviewed-by: default avatarScott Branden <sbranden@broadcom.com>
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      3bc2b234
  8. 06 Jan, 2016 2 commits
    • Grygorii Strashko's avatar
      PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD · 8ff0ef99
      Grygorii Strashko authored
      On -RT and if kernel is booting with "threadirqs" cmd line parameter,
      PCIe/PCI (MSI) IRQ cascade handlers (like dra7xx_pcie_msi_irq_handler())
      will be forced threaded and, as result, will generate warnings like this:
      
        WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 handle_irq_event_percpu+0x14c/0x174()
        irq 460 handler irq_default_primary_handler+0x0/0x14 enabled interrupts
        Backtrace:
         (warn_slowpath_common) from (warn_slowpath_fmt+0x38/0x40)
         (warn_slowpath_fmt) from (handle_irq_event_percpu+0x14c/0x174)
         (handle_irq_event_percpu) from (handle_irq_event+0x84/0xb8)
         (handle_irq_event) from (handle_simple_irq+0x90/0x118)
         (handle_simple_irq) from (generic_handle_irq+0x30/0x44)
         (generic_handle_irq) from (dra7xx_pcie_msi_irq_handler+0x7c/0x8c)
         (dra7xx_pcie_msi_irq_handler) from (irq_forced_thread_fn+0x28/0x5c)
         (irq_forced_thread_fn) from (irq_thread+0x128/0x204)
      
      This happens because all of them invoke generic_handle_irq() from the
      requested handler.  generic_handle_irq() grabs raw_locks and thus needs to
      run in raw-IRQ context.
      
      This issue was originally reproduced on TI dra7-evem, but, as was
      identified during discussion [1], other hosts can also suffer from this
      issue.  Fix all them at once by marking PCIe/PCI (MSI) IRQ cascade handlers
      IRQF_NO_THREAD explicitly.
      
      [1] http://lkml.kernel.org/r/1448027966-21610-1-git-send-email-grygorii.strashko@ti.com
      
      [bhelgaas: add stable tag, fix typos]
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Acked-by: Lucas Stach <l.stach@pengutronix.de> (for imx6)
      CC: stable@vger.kernel.org
      CC: Kishon Vijay Abraham I <kishon@ti.com>
      CC: Jingoo Han <jingoohan1@gmail.com>
      CC: Kukjin Kim <kgene@kernel.org>
      CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
      CC: Richard Zhu <Richard.Zhu@freescale.com>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: Simon Horman <horms@verge.net.au>
      CC: Pratyush Anand <pratyush.anand@gmail.com>
      CC: Michal Simek <michal.simek@xilinx.com>
      CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
      CC: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
      8ff0ef99
    • Christoph Biedl's avatar
      PCI: Fix minimum allocation address overwrite · 3460baa6
      Christoph Biedl authored
      Commit 36e097a8 ("PCI: Split out bridge window override of minimum
      allocation address") claimed to do no functional changes but unfortunately
      did: The "min" variable is altered.  At least the AVM A1 PCMCIA adapter was
      no longer detected, breaking ISDN operation.
      
      Use a local copy of "min" to restore the previous behaviour.
      
      [bhelgaas: avoid gcc "?:" extension for portability and readability]
      Fixes: 36e097a8 ("PCI: Split out bridge window override of minimum allocation address")
      Signed-off-by: default avatarChristoph Biedl <linux-kernel.bfrz@manchmal.in-ulm.de>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      CC: stable@vger.kernel.org      # v3.14+
      3460baa6
  9. 05 Jan, 2016 4 commits
  10. 11 Dec, 2015 8 commits