- 03 Oct, 2019 40 commits
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Le Ma authored
Front door firmware loading is done via the psp rather than the driver. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Needs more work to enable via front door loading. Signed-off-by:
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Tianci.Yin authored
load different cp firmware according to the DID and RID Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Allen Pais authored
alloc_workqueue is not checked for errors and as a result, a potential NULL dereference could occur. v2 (Felix Kuehling): * Fix compile error (kfifo_free instead of fifo_free) * Return proper error code Signed-off-by:
Allen Pais <allen.pais@oracle.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
Add new sections to amdgpu.rst, fix up formatting issues, add additional documentation to each section. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Fix DOC link name, clean up formatting in pp_dpm_* section. Acked-by:
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Alex Deucher authored
Fix parameters. Acked-by:
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Alex Deucher authored
Missing parameters, wrong comment type, etc. Acked-by:
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Alex Deucher authored
Document the new parameter. Fixes: 93065ac7 ("mm, oom: distinguish blockable mode for mmu notifiers") Acked-by:
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Alex Deucher authored
Drop extra function parameter. Acked-by:
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Harry Wentland authored
We had a couple of missing definitions and formatting errors. v2: Fix 'notifying' type Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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yu kuai authored
Fixes gcc warning: drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:431: warning: Excess function parameter 'sw' description in 'vcn_v2_5_disable_clock_gating' drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:550: warning: Excess function parameter 'sw' description in 'vcn_v2_5_enable_clock_gating' Fixes: cbead2bd ("drm/amdgpu: add VCN2.5 VCPU start and stop") Signed-off-by:
yu kuai <yukuai3@huawei.com> Signed-off-by:
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Arnd Bergmann authored
Without CONFIG_DEBUG_FS, we get a warning for an unused variable: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6020:33: error: unused variable 'source' [-Werror,-Wunused-variable] Hide the variable in an #ifdef like its only users. Fixes: 14b25846 ("drm/amd/display: add functionality to grab DPRX CRC entries.") Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Guchun Chen authored
Enable full ras by default, user does not need to enable it by boot parameter. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Jiange Zhao authored
Add Navi12 PCI id support. v2: flag as experimental for now (Alex) Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by:
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Tianci.Yin authored
update registers: mmUTCL1_CTRL Reviewed-by:
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Tianci.Yin authored
update registers: mmUTCL1_CTRL Reviewed-by:
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Alex Deucher authored
We can remove this later as things get closer to launch. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Alex Deucher authored
Otherwise we may get stale data. Reviewed-by:
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Alex Deucher authored
We need to make sure the fifo is flushed before we ask the psp to process the commands. Reviewed-by:
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Guchun Chen authored
No need to define the same variables in each loop of the function. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Guchun Chen authored
null ptr should be checked first to avoid null ptr access Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Hawking Zhang authored
For ASICs like renoir/arct, driver doesn't need to load mec2 jt. when mec1 jt is loaded, mec2 jt will be loaded automatically since the write is actaully broadcasted to both. We need to more time to test other gfx9 asic. but for now we should be able to draw conclusion that mec2 jt is not needed for renoir and arct. Signed-off-by:
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Hawking Zhang authored
enable psp block for firmware loading and other security feature setup. Signed-off-by:
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Kai-Heng Feng authored
Laptops with AMD APU doesn't restore display backlight brightness after system resume. This issue started when DC was introduced. Let's use BL_CORE_SUSPENDRESUME so the backlight core calls update_status callback after system resume to restore the backlight level. Tested on Dell Inspiron 3180 (Stoney Ridge) and Dell Latitude 5495 (Raven Ridge). Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Alex Deucher authored
We are reserving vram pages so they should be aligned to the GPU page size. Reviewed-by:
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Xiaojie Yuan authored
except soc_bounding_box which is not integrated in discovery table yet Signed-off-by:
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Tao Zhou authored
umc retired page belongs to vram and it should be aligned to gpu page size Signed-off-by:
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Prike Liang authored
VCN Gate/Ungate by processing the SMU power up/down message, otherwise S3 will resume failed as JPEG always power off during start VCN stage. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Tianci.Yin authored
Add Navi12 PCI id support. Reviewed-by:
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Tao Zhou authored
There are two cases of reserve error should be ignored: 1) a ras bad page has been allocated (used by someone); 2) a ras bad page has been reserved (duplicate error injection for one page); DRM_ERROR is unnecessary for the failure of bad page reserve Signed-off-by:
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Adam Zerella authored
Some of the documentation formatting could be improved which will resolve some Sphinx amdgpu build warnings e.g WARNING: Unexpected indentation. WARNING: Block quote ends without a blank line; unexpected unindent. WARNING: Inline emphasis start-string without end-string. Signed-off-by:
Adam Zerella <adam.zerella@gmail.com> Signed-off-by:
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Alex Deucher authored
Add new parameters. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Yong Zhao authored
These were deleted before, but somehow showed up again. Delete them again. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
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Bhawanpreet Lakha authored
[Why] HDCP is not fully finished, so we need to be able to build and run the driver without it. [How] Add a Kconfig to toggle it Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] We don't support HDCP for pre RAVEN asics [How] Check if we are RAVEN+. Use this to attach the content_protection property, this way usermode can't try to enable HDCP on pre DCN asics. Also we need to update the module on hpd so guard it aswell Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to use HW state to set content protection to ENABLED. This way we know that the link is encrypted from the HW side [How] Create a workqueue that queries the HW every ~2seconds, and sets it to ENABLED or DESIRED based on the result from the hardware Signed-off-by:
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Bhawanpreet Lakha authored
[Why] This is needed for DP as DP can send us info using irq. [How] Check if irq bit is set on short pulse and call the function that handles cpirq in amdgpu_dm_hdcp Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to manage the content protection property changes for different usecase, once cp is DESIRED we need to maintain the ENABLED/DESIRED status for different cases. [How] 1. Attach the content_protection property 2. HDCP enable (UNDESIRED -> DESIRED) call into the module with the correct parameters to start hdcp. Set cp to ENABLED 3. HDCP disable (ENABLED -> UNDESIRED) Call the module to disable hdcp. 3. Handle Special cases (Hotplug, S3, headless S3, DPMS) If already ENABLED: set to DESIRED on unplug/suspend/dpms, and disable hdcp Then on plugin/resume/dpms: enable HDCP Signed-off-by:
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