- 19 Dec, 2023 4 commits
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Konrad Dybcio authored
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 955f2ea3 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by:
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Konrad Dybcio authored
The PCIe GDSCs on most Qualcomm platforms expect the OS to always consider collapse requests as successful. This also concerns SM8550. Add the VOTABLE flag to the GDSCs in question to comply with these expectations. Fixes: 955f2ea3 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by:
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Konrad Dybcio authored
All of the 8550's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: 955f2ea3 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by:
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- 16 Dec, 2023 6 commits
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Dan Carpenter authored
If "regmap" is an error pointer then calling regmap_update_bits() will crash. We only need to call regmap_update_bits() if we had written to it earlier. Fixes: ff93872a ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/210d48ce-6ebc-4a6b-b30f-866d10d41a16@moroto.mountainSigned-off-by:
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Satya Priya Kakitapalli authored
Add runtime PM support to ensure the supply rails are enabled when necessary. Signed-off-by:
Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by:
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Satya Priya Kakitapalli authored
When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by:
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Satya Priya Kakitapalli authored
Add all the available resets for the video clock controller on sm8150. Fixes: 5658e8cf ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
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Bjorn Andersson authored
Merge SM8150 Video clock controller through a topic branch, to allow constants to be made available in the DeviceTree branch as well.
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Satya Priya Kakitapalli authored
Add all the available resets for the video clock controller on sm8150. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-1-56bec3a5e443@quicinc.comSigned-off-by:
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- 08 Dec, 2023 5 commits
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Rajendra Nayak authored
Adds the RPMH clocks present in X1E80100 SoC Co-developed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Rajendra Nayak authored
Add support for the global clock controller found on X1E80100 based devices. Co-developed-by:
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Bjorn Andersson authored
Merge the X1E80100 DeviceTree bindings through a topic branch, to allow the clock constants to be shared with the DeviceTree branch.
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Rajendra Nayak authored
Add bindings and update documentation for clock rpmh driver on X1E80100 SoCs. Signed-off-by:
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Rajendra Nayak authored
Add device tree bindings for global clock controller on X1E80100 SoCs. Signed-off-by:
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- 07 Dec, 2023 24 commits
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Imran Shaik authored
Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Acked-by:
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Taniya Das authored
Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the ECPI clock controller through a topic branch to make it possible to merge the clock constants into the DeviceTree branch as well.
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Imran Shaik authored
Add device tree bindings for qcom ecpri clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by:
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Satya Priya Kakitapalli authored
Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1 as per latest HW recommendation. Fixes: 0cef71f2 ("clk: qcom: Add graphics clock controller driver for SM8150") Signed-off-by:
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Neil Armstrong authored
Add RPMH Clocks for the SM8650 platform. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Neil Armstrong authored
Add Graphics Clock Controller (GPUCC) support for SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add Display Clock Controller (DISPCC) support for SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add TCSR Clock Controller support for SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add Global Clock Controller (GCC) driver plumbing for the SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add Global Clock Controller (GCC) tables for the SM8650 platform, the driver plumbing will be added afterwards. Reviewed-by:
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Bjorn Andersson authored
Merge SM8650 GCC, TCSRCC, DISPCC, GPUCC and RPMHCC bindings through a topic branch to make it possible to also merge and use the constants in the DeviceTree branch.
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Neil Armstrong authored
Add bindings documentation for the SM8650 RPMH Clock Controller. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Neil Armstrong authored
Add bindings documentation for the SM8650 Graphics Clock Controller. Reviewed-by:
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Neil Armstrong authored
Add bindings documentation for the SM8650 Display Clock Controller. Reviewed-by:
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Neil Armstrong authored
Add bindings documentation for the SM8650 General Clock Controller. Reviewed-by:
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Neil Armstrong authored
Add bindings documentation for the SM8650 TCSR Clock Controller. Signed-off-by:
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Vincent Knecht authored
When adding in the indexes for this clock-controller we missed GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK, GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK. Add them in now and rename ftbl_gcc_camss_csi0_1_clk to account for csi2 also using it. Reviewed-by:
Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.orgSigned-off-by:
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Vincent Knecht authored
When adding in the indexes for this clock-controller we missed GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK, GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK. Add them in now. Reviewed-by:
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Bryan O'Donoghue authored
Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage with additional CCI and IFE blocks and more granular clock parentage. Signed-off-by:
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Bjorn Andersson authored
Merge the SC8280XP Camera Clock Controller binding changes through a topic branch to allow them to be merged and used in the DeviceTree source branch as well.
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Bryan O'Donoghue authored
Add device tree bindings for the camera clock controller on Qualcomm SC8280XP platform. Signed-off-by:
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Bryan O'Donoghue authored
Various of the camcc bindings are repeated serially. We can use qcom,gcc.yaml to encapsulate the generic repeated patterns. Signed-off-by:
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Robert Marko authored
The Qualcomm IPQ6018 GCC clock controller has clock inputs, thus existing gcc-other.yaml was not describing it fully so move it to a separate schema. Fully document the allowed and required XO and sleep clock inputs, as well as update the provided example. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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- 03 Dec, 2023 1 commit
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Gokul Sriram Palanisamy authored
IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, add configuration values and the compatible. Co-developed-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by:
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Reviewed-by:
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