- 26 Sep, 2017 40 commits
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Andrey Grodzovsky authored
Headless mode set needs to be synchronized against outstanding nonblocking commits. This achieved by building atomic state and commiting it. v2: rebase on 4.11 Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
This reverts commit 0eb4667a073e. Signed-off-by:
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Andrey Grodzovsky authored
Modify amdgpu_dm_atomic_comit to implement atomic_comit_tail hook. Unify Buffer objects allocation and dealocation for surface updates and page flips. Simplify wait for fences and target_vbank logic for non blockiing commit. Remove hacky update surface to page flip synchronization we had and rely on atomic framework synchronization logic. v2: Add state->allow_modeset as indicator of page flip call. Signed-off-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Acked-by:
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Harry Wentland authored
Don't tell DRM otherwise. Signed-off-by:
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Charlene Liu authored
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Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
No need to assign them dynamically. This is much more readable. Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Harry Wentland authored
This doesn't show with gcc6 Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
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Harry Wentland authored
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Leon Elazar authored
1. dc: Adding missing mask for audio register DCCG_AUDIO_DTO_SOURCE 2. Changing the surface validation to check the limits of the clip rect instead of the source rect. Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Jordan Lazare authored
Gamma LUT shouldn't be used for 10-bit and above. Should instead be using prescale and bypassing input gamma. Signed-off-by:
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Amy Zhang authored
- Move PSR programming from link encoder to dmcu Signed-off-by:
Amy Zhang <Amy.Zhang@amd.com> Acked-by:
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Charlene Liu authored
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Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by:
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Charlene Liu authored
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Dmytro Laktyushkin authored
v2: agd: squash in the Makefile change as well. Signed-off-by:
Eagle Yeh <eagle.yeh@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
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Harry Wentland authored
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Charlene Liu authored
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Charlene Liu authored
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Charlene Liu authored
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Zeyu Fan authored
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Zeyu Fan <Zeyu.Fan@amd.com> Reviewed-by:
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Zeyu Fan authored
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Amy Zhang authored
- Source and destination color space should be the same for app control case - Bypass degamma, regamma, and gamut remap - Add hdr supported check for info frame Signed-off-by:
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Ken Chalmers authored
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Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Harry Wentland authored
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Jordan Lazare authored
When moving to a common dce/ infrastructure for all asics, some register fields do not exist in DCE8, and cause ASSERTS and debug spam. Instead, check to see whether a register field mask is valid before attempting to program the register field Signed-off-by:
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Harry Wentland authored
Also make the code somewhat more readable. Signed-off-by:
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Julia Lawall authored
Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by:
Julia Lawall <julia.lawall@lip6.fr> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Reviewed-by:
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Julia Lawall authored
Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by:
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Julia Lawall authored
Remove unneeded semicolons. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by:
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Jordan Lazare authored
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Zeyu Fan authored
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Charlene Liu authored
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