- 14 Aug, 2023 5 commits
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Konrad Dybcio authored
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by:Jeffrey Hugo <quic_jhugo@quicinc.com> Tested-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-4-6222fbc2916b@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
Up until now, we've been relying on some non-descript hardware magic to pinkypromise turn the clocks on for us. While new SoCs shine with that feature, MSM8998 can not always be fully trusted. Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual enable voting. Reviewed-by:
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Konrad Dybcio authored
We've not been consuming that clock for no apparent reason. Describe it. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
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Bjorn Andersson authored
Merge additional MSM8998 GCC DeviceTree binding constants through a topic branch to make them available to the DeviceTree source tree as well.
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Konrad Dybcio authored
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by:
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- 11 Aug, 2023 3 commits
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Sricharan Ramabadhran authored
Add support for the global clock controller found on IPQ5018 based devices. Acked-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.comSigned-off-by:
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Bjorn Andersson authored
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
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Sricharan Ramabadhran authored
This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by:
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- 04 Aug, 2023 2 commits
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Luca Weiss authored
GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae9 ("clk: qcom: Add SM6350 GCC driver") Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Konrad Dybcio authored
Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by:
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- 03 Aug, 2023 3 commits
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Arnd Bergmann authored
The SM_GCC_8550 symbol and others can only be built for ARM64 or when compile testing, but it gets selected by other drivers that can also be built for 32-bit ARCH_QCOM when not compile testing, which results in a Kconfig warning: WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n]) Selected by [m]: - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] Add further 'depends on' statements to tighten this in a way that avoids the missing dependencies. Fixes: fd0b5b10 ("clk: qcom: Introduce SM8350 VIDEOCC") Fixes: 441fe711 ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450") Fixes: f53153a3 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
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Patrick Whewell authored
GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e577092 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Patrick Whewell <patrick.whewell@sightlineapplications.com> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230802210359.408-1-patrick.whewell@sightlineapplications.comSigned-off-by:
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Yang Yingliang authored
The pxo_parent_data inroduced in commit bac4675a ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Reviewed-by:
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- 31 Jul, 2023 13 commits
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David Wronek authored
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by:
David Wronek <davidwronek@gmail.com> Reviewed-by:
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Yassine Oudjana authored
The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230527093934.101335-4-y.oudjana@protonmail.comSigned-off-by:
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Yassine Oudjana authored
The CBF clock on MSM8996 Pro has a different divisor compared to MSM8996 and is therefore not fully compatible with it. Add a new compatible string to differentiate between them. Signed-off-by:
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Dmitry Baryshkov authored
The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by:
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Dmitry Baryshkov authored
The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6 ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by:
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Dmitry Baryshkov authored
The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by:
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Dmitry Baryshkov authored
The global clock controller on MDM9615 uses external CXO and PLL7 clocks. Split the qcom,gcc-mdm9615 to the separate schema file. Reviewed-by:
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Dmitry Baryshkov authored
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by:
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Dmitry Baryshkov authored
Describe parent clocks used by the LCC on the MDM9615 platform. It is the list as the one for msm8960/apq8064, with only difference being pxo/cxo replacement. Acked-by:
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Konrad Dybcio authored
SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by:
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Konrad Dybcio authored
SC8280XP reuses the SM8350 video clock controller block, changing just a couple tunables. Docuemnt it. Acked-by:
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- 28 Jul, 2023 1 commit
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Konrad Dybcio authored
The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76f ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by:
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- 18 Jul, 2023 8 commits
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 892df019 ("clk: qcom: Add QCS404 TuringCC") Cc: stable@vger.kernel.org # 5.2 Cc: Bjorn Andersson <andersson@kernel.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-9-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 8def929c ("clk: qcom: Add modem clock controller driver for SC7180") Cc: stable@vger.kernel.org # 5.7 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 6cdef273 ("clk: qcom: Add Q6SSTOP clock controller for QCS404") Cc: stable@vger.kernel.org # 5.5 Signed-off-by:
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 4ab43d17 ("clk: qcom: Add lpass clock controller driver for SC7280") Cc: stable@vger.kernel.org # 5.16 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Johan Hovold authored
Make sure to decrement the runtime PM usage count before returning in case RCG dynamic frequency switch initialisation fails. Fixes: 2a541abd ("clk: qcom: gcc-sc8280xp: Add runtime PM") Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Johan Hovold authored
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 90114ca1 ("clk: qcom: add SM8550 DISPCC driver") Cc: stable@vger.kernel.org # 6.3 Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Johan Hovold authored
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 16fb89f9 ("clk: qcom: Add support for Display Clock Controller on SM8450") Cc: stable@vger.kernel.org # 6.1 Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Johan Hovold authored
To make sure that the controller is runtime resumed and its power domain is enabled before accessing its registers during probe, the synchronous runtime PM interface must be used. Fixes: 8d402594 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Cc: stable@vger.kernel.org # 5.11 Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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- 15 Jul, 2023 5 commits
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Bjorn Andersson authored
This series reshuffles things around, moving the management of SMD RPM bus clocks to the interconnect framework where they belong. This helps us solve a couple of issues: 1. We can work towards unused clk cleanup of RPMCC without worrying about it killing some NoC bus, resulting in the SoC dying. Deasserting actually unused RPM clocks (among other things) will let us achieve "true SoC-wide power collapse states", also known as VDD_LOW and VDD_MIN. 2. We no longer have to keep tons of quirky bus clock ifs in the icc driver. You either have a RPM clock and call "rpm set rate" or you have a single non-RPM clock (like AHB_CLK_SRC) or you don't have any. 3. There's less overhead - instead of going through layers and layers of the CCF, ratesetting comes down to calling max() and sending a single RPM message. ICC is very very dynamic so that's a big plus. The clocks still need to be vaguely described in the clk-smd-rpm driver, as it gives them an initial kickoff, before actually telling RPM to enable DVFS scaling. After RPM receives that command, all clocks that have not been assigned a rate are considered unused and are shut down in hardware, leading to the same issue as described in point 1. We can consider marking them __initconst in the future, but this series is very fat even without that.. Apart from that, it squashes a couple of bugs that really need fixing.. The series is merged through a topic branch to manage the dependencies between interconnect, Qualcomm clocks and Qualcomm SoC.
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Konrad Dybcio authored
Up until now, we've been aggregating the bandwidth values and only dividing them by the bus width of the source node. This was completely wrong, as different nodes on a given path may (and usually do) have varying bus widths. That in turn, resulted in the calculated clock rates being completely bogus - usually they ended up being much higher, as NoC_A<->NoC_B links are very wide. Since we're not using the aggregate bandwidth value for anything other than clock rate calculations, remodel qcom_icc_bus_aggregate() to calculate the per-context clock rate for a given provider, taking into account the bus width of every individual node. Fixes: 30c8fa3e ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reported-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Georgi Djakov <djakov@kernel.org> Link: https://lore.kernel.org/r/20230526-topic-smd_icc-v7-22-09c78c175546@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Currently, we're setting the aggregated-on-provider bandwidth on each node, individually. That is of course incorrect and results in far too high votes. Use the correct values to ensure we're not wasting power. Fixes: 30c8fa3e ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reported-by:
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Konrad Dybcio authored
Up until now, for some reason we've only been setting bandwidth values on the active-only context. That pretty much meant that RPM could lift all votes when entering sleep mode. Or never sleep at all. That in turn could potentially break things like USB wakeup, as the connection between APSS and SNoC/PNoC would simply be dead. Set the values appropriately. Fixes: 30c8fa3e ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reviewed-by:
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Konrad Dybcio authored
SMD RPM only provides two buckets, one each for the active-only and active-sleep RPM contexts. Use the correct constant to allocate and operate on them. This will make the qcom,icc.h header no longer work with this driver, mostly because.. it was never meant to! The commit that introduced bucket support to SMD RPM was trying to shove a square into a round hole and it did not work out very well. That said, there are no active users of SMD RPM ICC + qcom,icc.h, so that doesn't hurt. Fixes: dcbce7b0 ("interconnect: qcom: icc-rpm: Support multiple buckets") Reviewed-by:
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