- 10 Oct, 2023 22 commits
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Georgi Djakov authored
* icc-misc interconnect: imx: Replace custom implementation of COUNT_ARGS() interconnect: msm8974: Replace custom implementation of COUNT_ARGS() interconnect: qcom: osm-l3: Replace custom implementation of COUNT_ARGS() interconnect: fix error handling in qnoc_probe() interconnect: imx: Replace inclusion of kernel.h in the header dt-bindings: interconnect: qcom,rpmh: do not require reg on SDX65 MC virt Signed-off-by:Georgi Djakov <djakov@kernel.org>
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Krzysztof Kozlowski authored
The MC virt interconnect in SDX65 DTSI does not have reg. Similarly in the downstream DTS, thus assume this is an interconnect without own dedicated IO address space. This fixes dtbs_check warnings like: qcom-sdx65-mtp.dtb: interconnect-mc-virt: 'reg' is a required property Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230827114026.47806-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Andy Shevchenko authored
The kernel.h is not used here directly, replace it with proper set of headers. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230920153645.2068193-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Yang Yingliang authored
Add missing clk_disable_unprepare() and clk_bulk_disable_unprepare() in the error path in qnoc_probe(). And when qcom_icc_qos_set() fails, it needs remove nodes and disable clks. Fixes: 2e2113c8 ("interconnect: qcom: rpm: Handle interface clocks") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230803130521.959487-1-yangyingliang@huawei.comSigned-off-by:
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Andy Shevchenko authored
Replace custom and non-portable implementation of COUNT_ARGS(). Fixes: 5bc9900a ("interconnect: qcom: Add OSM L3 interconnect provider support") Signed-off-by:
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Andy Shevchenko authored
Replace custom and non-portable implementation of COUNT_ARGS(). Fixes: 4e60a956 ("interconnect: qcom: add msm8974 driver") Signed-off-by:
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Andy Shevchenko authored
Replace custom and non-portable implementation of COUNT_ARGS(). Fixes: f0d80485 ("interconnect: Add imx core driver") Signed-off-by:
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Georgi Djakov authored
Add interconnect driver support for SDX75 platform. * icc-sdx75 dt-bindings: interconnect: Add compatibles for SDX75 interconnect: qcom: Add SDX75 interconnect provider driver Link: https://lore.kernel.org/r/1694614256-24109-1-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>anter a commit message to explain why this merge is necessary,
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Georgi Djakov authored
In the downstream kernel, ACV enable_mask has not been mentioned explicitly, rather being handled by a sneaky if-condition [1], [2]. Add it to all RPMh platforms to actually enable that BCM. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L556-567 [2] https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L475-495 * icc-acv-enable-mask interconnect: qcom: qdu1000: Set ACV enable_mask interconnect: qcom: sc7180: Set ACV enable_mask interconnect: qcom: sc7280: Set ACV enable_mask interconnect: qcom: sc8180x: Set ACV enable_mask interconnect: qcom: sc8280xp: Set ACV enable_mask interconnect: qcom: sdm670: Set ACV enable_mask interconnect: qcom: sdm845: Set ACV enable_mask interconnect: qcom: sm6350: Set ACV enable_mask interconnect: qcom: sm8150: Set ACV enable_mask interconnect: qcom: sm8250: Set ACV enable_mask interconnect: qcom: sm8350: Set ACV enable_mask Link: https://lore.kernel.org/r/20230811-topic-acv-v2-0-765ad70e539a@linaro.orgSigned-off-by:
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Rohit Agarwal authored
Add driver for the Qualcomm interconnect buses found in SDX75. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/1694614256-24109-3-git-send-email-quic_rohiagar@quicinc.comSigned-off-by:
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Rohit Agarwal authored
Add dt-bindings compatibles and interconnect IDs for Qualcomm SDX75 platform. Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: d26a5667 ("interconnect: qcom: Add SM8350 interconnect provider driver") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 6df5b349 ("interconnect: qcom: Add SM8250 interconnect provider driver") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: a09b817c ("interconnect: qcom: Add SM8150 interconnect provider driver") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 6a6eff73 ("interconnect: qcom: Add SM6350 driver support") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: b5d2f741 ("interconnect: qcom: Add sdm845 interconnect provider driver") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 7e438e18 ("interconnect: qcom: add sdm670 interconnects") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: f29dabda ("interconnect: qcom: Add SC8280XP interconnect provider") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 9c8c6bac ("interconnect: qcom: Add SC8180x providers") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 46bdcac5 ("interconnect: qcom: Add SC7280 interconnect provider driver") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 2d1f95ab ("interconnect: qcom: Add SC7180 interconnect provider driver") Signed-off-by:
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Konrad Dybcio authored
ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 1f51339f ("interconnect: qcom: Add QDU1000/QRU1000 interconnect driver") Signed-off-by:
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- 09 Oct, 2023 18 commits
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Georgi Djakov authored
The recent necessary overhaul [1] of how we represent SMD ICC and RPM bus clocks changed the way they're connected. The bindings however were not updated to reflect that. This series tries to address that, while also making the relevant bindings less convoluted. Now, instead of referencing RPM SMD bus clocks via clocks=<>, they're handled internally within the interconnect framework (via direct RPM calls from there). We still need to allow some "interface" clocks, which are necessary to access some registers and not managed for us. [1] https://lore.kernel.org/linux-arm-msm/20230526-topic-smd_icc-v7-0-09c78c175546@linaro.org/ * icc-rpm-dt-bindings dt-bindings: interconnect: qcom: Introduce qcom,rpm-common dt-bindings: interconnect: qcom: qcm2290: Remove RPM bus clocks dt-bindings: interconnect: qcom: Fix and separate out SDM660 dt-bindings: interconnect: qcom: Fix and separate out MSM8996 dt-bindings: interconnect: qcom: Fix and separate out MSM8939 dt-bindings: interconnect: qcom: rpm: Clean up the file dt-bindings: interconnect: qcom: rpm: Clean up the example Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-0-e33d5acbf3bd@linaro.orgSigned-off-by:
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Konrad Dybcio authored
One example is enough, remove the others and fix up the indentation while at it. Signed-off-by:
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Konrad Dybcio authored
Following the recent cleanups and untanglements, remove abusive direct references to RPM bus clocks, include the rpm-common YAML and update Georgi's email. Signed-off-by:
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Konrad Dybcio authored
Separate out MSM8939 icc bindings from the common file and fix the clocks description by removing the wrong internal RPM bus clock representation that we've been carrying for years. This was the final one, so also retire the shared file. Signed-off-by:
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Konrad Dybcio authored
Separate out MSM8996 icc bindings from the common file and fix the clocks description by removing the wrong internal RPM bus clock representation that we've been carrying for years. Signed-off-by:
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Konrad Dybcio authored
Separate out SDM660 icc bindings from the common file and fix the clocks description by removing the wrong internal RPM bus clock representation that we've been carrying for years. Signed-off-by:
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Konrad Dybcio authored
After the recent reshuffling, bus clocks are no longer exposed as RPM clocks. Remove the old description. Reviewed-by:
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Konrad Dybcio authored
The current RPM interconnect bindings are messy. Start cleaning them up with a common include. Signed-off-by:
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Georgi Djakov authored
Certain platforms require that some buses (or individual nodes) make some additional changes to the clock rate formula, throwing in some magic, Qualcomm-defined coefficients, to account for "inefficiencies". Add the framework for it and utilize it on a couple SoCs. * icc-qcom-coefficients interconnect: qcom: icc-rpm: Add AB/IB calculations coefficients interconnect: qcom: icc-rpm: Separate out clock rate calulcations interconnect: qcom: icc-rpm: Let nodes drive their own bus clock interconnect: qcom: icc-rpm: Check for node-specific rate coefficients interconnect: qcom: qcm2290: Hook up MAS_APPS_PROC's bus clock interconnecga qcom: qcm2290: Set AB coefficients interconnecgg acom: qcm2290: Update EBI channel configuration interconnect: qcom: sdm660: Set AB/IB coefficients interconnect: qcom: msm8996: Set AB/IB coefficients Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-0-c04b60caa467@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Some buses and nodes need additional manual adjustments atop the usual calculations. Fill in the missing coefficients. Signed-off-by:
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Konrad Dybcio authored
Some buses and nodes need additional manual adjustments atop the usual calculations. Fill in the missing coefficients. Signed-off-by:
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Konrad Dybcio authored
QCM2290 can support two memory configurations: single-channel, 32-bit wide LPDDR3 @ up to 933MHz (bus clock) or dual-channel, 16-bit wide LPDDR4X @ up to 1804 MHz. The interconnect driver in its current form seems to gravitate towards the first one, however there are no LPDDR3- equipped boards upstream and we still don't have a great way to discern the DDR generations on the kernel side. To make DDR scaling possible on the only currently-supported 2290 board, stick with the LPDDR4X config by default. The side effect on any potential LPDDR3 board would be that the requested bus clock rate is too high (but still capped to the firmware-configured FMAX). Signed-off-by:
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Konrad Dybcio authored
Some buses need additional manual adjustments atop the usual calculations. Fill in the missing coefficients. Signed-off-by:
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Konrad Dybcio authored
This single node has its own clock which seems to be responsible for transactions between CPUSS (CPU + some stuff) and the GNOC. See [1] for reference. Define it and hook it up. [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/02f8c342b23c20a5cf967df649814be37a08227c%5E%21/#F0Signed-off-by:
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Konrad Dybcio authored
Some nodes may have different coefficients than the general values for bus they're attached to. Check for that and use them if present. See [1], [2] for reference. [1] https://github.com/sonyxperiadev/kernel/commit/7456d9779af9ad6bb9c7ee6f33d5c5a8d3648e24 [2] https://github.com/artem/android_kernel_sony_msm8996/commit/bf7a8985dcaf0eab5bc2562d2d6775e7e29c0f30Signed-off-by:
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Konrad Dybcio authored
If this hardware couldn't get messier, some nodes are supposed to drive their own bus clock.. Presumably to connect to some intermediate interface between the node itself and the bus it's (supposed to be) connected to. Expand the node struct with the necessary data and hook up the allocations & calculations. Note that the node-specific AB/IB coefficients contribute (by design) to both the node-level and the bus-level aggregation. Signed-off-by:
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Konrad Dybcio authored
In preparation for also setting per-node clock rates, separate out the logic that computes it. Signed-off-by:
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Konrad Dybcio authored
Presumably due to the hardware being so complex, some nodes (or busses) have different (usually higher) requirements for bandwidth than what the usual calculations would suggest. Looking at the available downstream files, it seems like AB values are adjusted per-bus and IB values are adjusted per-node. With that in mind, introduce percentage-based coefficient struct members and use them in the calculations. One thing to note is that the IB coefficient is inverse (100/ib_percent) which feels a bit backwards, but it's necessary for precision.. Signed-off-by:
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