- Disable PHY when j721e_pcie_probe() fails after initializing it
  (Christophe JAILLET)

- Return success when cdns-pcie probe succeeds instead of doing error
  cleanup (Li Chen)

* pci/host/cadence:
  PCI: cadence: Add cdns_plat_pcie_probe() missing return
  PCI: j721e: Fix j721e_pcie_probe() error path

- Make of_phandle_args_to_fwspec() generally available (Marc Zyngier)

- Allow matching of interrupt-maps local to interrupt controller or PCI
  device (Marc Zyngier)

- Add Apple SoC (e.g., M1) PCIe host controller driver, which enables
  access to USB type-A, Ethernet, Wi-Fi, Bluetooth devices; these require
  additional drivers of their own (Alyssa Rosenzweig)

- Add apple INTx, per-port, and MSI interrupt support (Marc Zyngier)

- Configure apple Requester-ID-to-Stream-ID mapper for IOMMU (DART) support
  (Marc Zyngier)

* pci/host/apple:
  PCI: apple: Configure RID to SID mapper on device addition
  iommu/dart: Exclude MSI doorbell from PCIe device IOVA range
  PCI: apple: Implement MSI support
  PCI: apple: Add INTx and per-port interrupt support
  PCI: apple: Set up reference clocks when probing
  PCI: apple: Add initial hardware bring-up
  PCI: of: Allow matching of an interrupt-map local to a PCI device
  of/irq: Allow matching of an interrupt-map local to an interrupt controller
  irqdomain: Make of_phandle_args_to_fwspec() generally available

- Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár)

- Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár)

- Downgrade PIO Response Status messages to debug level (Marek Behún)

- Preserve CRS SV (Config Request Retry Software Visibility) bit in
  emulated Root Control register (Pali Rohár)

- Fix issue in configuring reference clock (Pali Rohár)

- Don't clear status bits for masked interrupts (Pali Rohár)

- Don't mask unused interrupts (Pali Rohár)

- Avoid code repetition in advk_pcie_rd_conf() (Marek Behún)

- Retry config accesses on CRS response (Pali Rohár)

- Simplify emulated Root Capabilities initialization (Pali Rohár)

- Fix several link training issues (Pali Rohár)

- Fix link-up checking via LTSSM (Pali Rohár)

- Fix reporting of Data Link Layer Link Active (Pali Rohár)

- Fix emulation of W1C bits (Marek Behún)

- Fix MSI domain .alloc() method to return zero on success (Marek Behún)

- Read entire 16-bit MSI vector in MSI handler, not just low 8 bits (Marek
  Behún)

- Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits at
  startup; PCI core will set those as necessary (Pali Rohár)

- When operating as a Root Port, set class code to "PCI Bridge" instead of
  the default "Mass Storage Controller" (Pali Rohár)

- Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't
  implement this per spec (Pali Rohár)

- Add emulation of option ROM BAR since aardvark doesn't implement this per
  spec (Pali Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge
  PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
  PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge
  PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge
  PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG
  PCI: aardvark: Fix return value of MSI domain .alloc() method
  PCI: pci-bridge-emul: Fix emulation of W1C bits
  PCI: aardvark: Fix reporting Data Link Layer Link Active
  PCI: aardvark: Fix checking for link up via LTSSM state
  PCI: aardvark: Fix link training
  PCI: aardvark: Simplify initialization of rootcap on virtual bridge
  PCI: aardvark: Implement re-issuing config requests on CRS response
  PCI: aardvark: Deduplicate code in advk_pcie_rd_conf()
  PCI: aardvark: Do not unmask unused interrupts
  PCI: aardvark: Do not clear status bits of masked interrupts
  PCI: aardvark: Fix configuring Reference clock
  PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge
  PCI: aardvark: Don't spam about PIO Response Status
  PCI: aardvark: Fix PCIe Max Payload Size setting
  PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros

- Tidy setup-irq.c comments (Pranay Sanghai)

- Fix misspellings (Krzysztof Wilczyński)

- Fix sprintf(), sscanf() format mismatches (Krzysztof Wilczyński)

- Tidy cpqphp code formatting (Krzysztof Wilczyński)

- Remove unused pci_pool wrappers, which have been replaced by dma_pool
  (Cai Huoqing)

- Remove a redundant initialization in __pci_reset_function_locked() (Colin
  Ian King)

- Use 'unsigned int' instead of 'unsigned' (Krzysztof Wilczyński)

- Update PCI subsystem information in MAINTAINERS (Krzysztof Wilczyński)

- Include generic <linux/> headers instead of <asm/> for cpqphp and vmd
  (Krzysztof Wilczyński)

* pci/misc:
  PCI: vmd: Drop redundant includes of <asm/device.h>, <asm/msi.h>
  PCI: cpqphp: Use <linux/io.h> instead of <asm/io.h>
  MAINTAINERS: Update PCI subsystem information
  PCI: Prefer 'unsigned int' over bare 'unsigned'
  PCI: Remove redundant 'rc' initialization
  PCI: Remove unused pci_pool wrappers
  PCI: cpqphp: Format if-statement code block correctly
  PCI: Use unsigned to match sscanf("%x") in pci_dev_str_match_path()
  PCI: hv: Remove unnecessary use of %hx
  PCI: Correct misspelled and remove duplicated words
  PCI: Tidy comments

- Add pci_read_vpd_any(), pci_write_vpd_any() to access VPD at arbitrary
  offsets (Heiner Kallweit)

- Use VPD API to replace custom code in cxgb3 driver (Heiner Kallweit)

* pci/vpd:
  cxgb3: Remove seeprom_write and use VPD API
  cxgb3: Use VPD API in t3_seeprom_wp()
  cxgb3: Remove t3_seeprom_read and use VPD API
  PCI/VPD: Use pci_read_vpd_any() in pci_vpd_size()
  PCI/VPD: Add pci_read/write_vpd_any()

- Avoid bus resets on Atheros QCA6174, since they hang (Ingmar Klein)

- Use store and forward mode on Pericom PI7C9X2G switches to avoid ACS
  erratum with ACS P2P Request Redirect (Nathan Rossi)

* pci/virtualization:
  PCI: Add ACS quirk for Pericom PI7C9X2G switches
  PCI: Mark Atheros QCA6174 to avoid bus reset

- Check for CAP_SYS_ADMIN before validating sysfs user input, not after
  (Krzysztof Wilczyński)

- Always return -EINVAL from sysfs "store" functions for invalid user input
  instead of -EINVAL sometimes and -ERANGE others (Krzysztof Wilczyński)

- Use kstrtobool() directly instead of the strtobool() wrapper (Krzysztof
  Wilczyński)

* pci/sysfs:
  PCI: Use kstrtobool() directly, sans strtobool() wrapper
  PCI/sysfs: Return -EINVAL consistently from "store" functions
  PCI/sysfs: Check CAP_SYS_ADMIN before parsing user input

# Conflicts:
#	drivers/pci/iov.c

- Return error to application when command execution fails because an
  out-of-band reset has cleared the device BARs, Memory Space Enable, etc
  (Kelvin Cao)

- Fix MRPC error status handling issue (Kelvin Cao)

- Mask out other bits when reading of management VEP instance ID (Kelvin
  Cao)

- Return EOPNOTSUPP instead of ENOTSUPP from sysfs show functions (Kelvin
  Cao)

- Add check of event support (Logan Gunthorpe)

* pci/switchtec:
  PCI/switchtec: Add check of event support
  PCI/switchtec: Replace ENOTSUPP with EOPNOTSUPP
  PCI/switchtec: Update the way of getting management VEP instance ID
  PCI/switchtec: Fix a MRPC error status handling issue
  PCI/switchtec: Error out MRPC execution when MMIO reads fail

- Coalesce host bridge contiguous apertures to allow P2P bridge windows
  that span several contiguous host bridge apertures (Kai-Heng Feng)

* pci/resource:
  PCI: Coalesce host bridge contiguous apertures

- Don't setup portdrv IRQs if there are no port drivers that use them, to
  conserve vectors and avoid spurious events (Jan Kiszka)

* pci/portdrv:
  PCI/portdrv: Do not setup up IRQs if there are no users

- Apply bus offset correctly in DMA address calculation, which used the
  wrong sign before (Wang Lu)

* pci/p2pdma:
  PCI/P2PDMA: Apply bus offset correctly in DMA address calculation

- Document sysfs "irq" attribute, which contains either the INTx IRQ (the
  intended behavior) or the first MSI IRQ (historical mistake retained for
  backwards compatibility) (Barry Song)

- Rework "irq" sysfs show function to explicitly fetch first MSI IRQ
  instead of depending on core to put it in dev->irq, to enable future core
  cleanup (Barry Song)

* pci/msi:
  PCI/sysfs: Explicitly show first MSI IRQ for 'irq'
  PCI: Document /sys/bus/pci/devices/.../irq

- Ignore Link Down/Up caused by error-induced Hot Reset so endpoint driver
  can remain bound to device during error recovery (Lukas Wunner)

- Remove unused resume err_handler (Lukas Wunner)

- Remove unused pcie_port_bus_{,un}register() declarations (Lukas Wunner)

- Skip compiling err.c when CONFIG_PCIEAER not set (Lukas Wunner)

* pci/hotplug:
  PCI/ERR: Reduce compile time for CONFIG_PCIEAER=n
  PCI/portdrv: Remove unused pcie_port_bus_{,un}register() declarations
  PCI/portdrv: Remove unused resume err_handler
  PCI: pciehp: Ignore Link Down/Up caused by error-induced Hot Reset
  PCI/portdrv: Rename pm_iter() to pcie_port_device_iter()

- Drop the struct pci_dev.driver pointer, which is redundant with the
  struct device.driver pointer (Uwe Kleine-König)

* pci/driver:
  PCI: Remove struct pci_dev->driver
  PCI: Use to_pci_driver() instead of pci_dev->driver
  x86/pci/probe_roms: Use to_pci_driver() instead of pci_dev->driver
  perf/x86/intel/uncore: Use to_pci_driver() instead of pci_dev->driver
  powerpc/eeh: Use to_pci_driver() instead of pci_dev->driver
  usb: xhci: Use to_pci_driver() instead of pci_dev->driver
  cxl: Use to_pci_driver() instead of pci_dev->driver
  cxl: Factor out common dev->driver expressions
  xen/pcifront: Use to_pci_driver() instead of pci_dev->driver
  xen/pcifront: Drop pcifront_common_process() tests of pcidev, pdrv
  nfp: use dev_driver_string() instead of pci_dev->driver->name
  mlxsw: pci: Use dev_driver_string() instead of pci_dev->driver->name
  net: marvell: prestera: use dev_driver_string() instead of pci_dev->driver->name
  net: hns3: use dev_driver_string() instead of pci_dev->driver->name
  crypto: hisilicon - use dev_driver_string() instead of pci_dev->driver->name
  powerpc/eeh: Use dev_driver_string() instead of struct pci_dev->driver->name
  ssb: Use dev_driver_string() instead of pci_dev->driver->name
  bcma: simplify reference to driver name
  crypto: qat - simplify adf_enable_aer()
  scsi: message: fusion: Remove unused mpt_pci driver .probe() 'id' parameter
  PCI/ERR: Factor out common dev->driver expressions
  PCI: Drop pci_device_probe() test of !pci_dev->driver
  PCI: Drop pci_device_remove() test of pci_dev->driver
  PCI: Return NULL for to_pci_driver(NULL)

- Rename pcibios_add_device() to pcibios_device_add() since it's called
  from pci_device_add() (Oliver O'Halloran)

- Don't try to enable AtomicOps on VFs, since they can only be enabled on
  the PF (Selvin Xavier)

* pci/enumeration:
  PCI: Do not enable AtomicOps on VFs
  PCI: Rename pcibios_add_device() to pcibios_device_add()

- Re-enable LTR in Downstream Ports after it has been disabled by reset or
  hotplug to allow use of ASPM L1.2 again and prevent Unsupported Request
  errors when Endpoint sends LTR messages (Mingchuang Qiao)

* pci/aspm:
  PCI: Re-enable Downstream Port LTR after reset or hotplug

- Simplify _OSC negotiation with platform for control of PCIe features
  (Joerg Roedel)

* pci/acpi:
  PCI/ACPI: Check for _OSC support in acpi_pci_osc_control_set()
  PCI/ACPI: Move _OSC query checks to separate function
  PCI/ACPI: Move supported and control calculations to separate functions
  PCI/ACPI: Remove OSC_PCI_SUPPORT_MASKS and OSC_PCI_CONTROL_MASKS

The Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 PCIe switches have an
erratum for ACS P2P Request Redirect behaviour when used in the cut-through
forwarding mode. The recommended work around for this issue is to use the
switch in store and forward mode. The erratum results in packets being
queued and not being delivered upstream, which can be observed as very poor
downstream device performance and/or dropped device-generated
data/interrupts.

Add a fixup so that when enabling or resuming the downstream port we check
if it has enabled ACS P2P Request Redirect, and if so, change the device
(via the upstream port) to use the store and forward operating mode.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=177471
Link: https://lore.kernel.org/r/20210910025823.196508-1-nathan@nathanrossi.comTested-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Nathan Rossi <nathan.rossi@digi.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

The Apple PCIe controller doesn't directly feed the endpoint's Requester ID
to the IOMMU (DART), but instead maps RIDs onto Stream IDs (SIDs). The DART
and the PCIe controller must thus agree on the SIDs that are used for
translation (by using the 'iommu-map' property).

For this purpose, parse the 'iommu-map' property each time a device gets
added, and use the resulting translation to configure the PCIe RID-to-SID
mapper. Similarly, remove the translation if/when the device gets removed.

This is all driven from a bus notifier which gets registered at probe time.
Hopefully this is the only PCI controller driver in the whole system.

[bhelgaas: squash indentation from Zhaoyu Liu <zackary.liu.pro@gmail.com>:
https://lore.kernel.org/r/20211031135544.GA1616@pc]
Link: https://lore.kernel.org/r/20210929163847.2807812-10-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>

The MSI doorbell on Apple HW can be any address in the low 4GB range.
However, the MSI write is matched by the PCIe block before hitting the
iommu. It must thus be excluded from the IOVA range that is assigned to any
PCIe device.

Link: https://lore.kernel.org/r/20210929163847.2807812-9-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>

Probe for the 'msi-ranges' property, and implement the MSI support in the
form of the usual two-level hierarchy.

Note that contrary to the wired interrupts, MSIs are shared among all the
ports.

Link: https://lore.kernel.org/r/20210929163847.2807812-8-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Add support for the per-port interrupt controller that deals with both INTx
signalling and management interrupts.

This allows the Link-up/Link-down interrupts to be wired, allowing the
bring-up to be synchronised (and provide debug information).  The framework
can further be used to handle the rest of the per port events if and when
necessary.

Likewise, INTx signalling is implemented so that end-points can actually be
used.

Link: https://lore.kernel.org/r/20210929163847.2807812-7-maz@kernel.org
Link: https://lore.kernel.org/r/20211004150552.3844830-1-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Apple's PCIe controller requires clocks to be configured in order to
bring up the hardware. Add the register pokes required to do so.

Adapted from Corellium's driver via Mark Kettenis's U-Boot patches.
Co-developed-by: Stan Skowronek <stan@corellium.com>
Link: https://lore.kernel.org/r/20210929163847.2807812-6-maz@kernel.orgSigned-off-by: Stan Skowronek <stan@corellium.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Add a minimal driver to bring up the PCIe bus on Apple system-on-chips,
particularly the Apple M1. This driver exposes the internal bus used for
the USB type-A ports, Ethernet, Wi-Fi, and Bluetooth. Bringing up the
radios requires additional drivers beyond what's necessary for PCIe itself.
Co-developed-by: Stan Skowronek <stan@corellium.com>
Link: https://lore.kernel.org/r/20210929163847.2807812-5-maz@kernel.orgSigned-off-by: Stan Skowronek <stan@corellium.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>

Just as we now allow an interrupt map to be parsed when part of an
interrupt controller, there is no reason to ignore an interrupt map that
would be part of a pci device node such as a root port since we already
allow interrupt specifiers.

Allow the matching of such property when local to the node of a PCI
device, which allows the device itself to use the interrupt map for for
its own purpose.

Link: https://lore.kernel.org/r/20210929163847.2807812-4-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>

of_irq_parse_raw() has a baked assumption that if a node has an
interrupt-controller property, it cannot possibly also have an
interrupt-map property (the latter being ignored).

This seems to be an odd behaviour, and there is no reason why we should
avoid supporting this use case. This is specially useful when a PCI root
port acts as an interrupt controller for PCI endpoints, such as this:

  pcie0: pcie@690000000 {
      [...]
      port00: pci@0,0 {
	  device_type = "pci";
	  [...]
	  #address-cells = <3>;

	  interrupt-controller;
	  #interrupt-cells = <1>;

	  interrupt-map-mask = <0 0 0 7>;
	  interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
			  <0 0 0 2 &port00 0 0 0 1>,
			  <0 0 0 3 &port00 0 0 0 2>,
			  <0 0 0 4 &port00 0 0 0 3>;
      };
  };

Handle it by detecting that we have an interrupt-map early in the parsing,
and special case the situation where the phandle in the interrupt map
refers to the current node (which is the interesting case here).

Link: https://lore.kernel.org/r/20210929163847.2807812-3-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>

of_phandle_args_to_fwspec() can be generally useful to code extracting a DT
of_phandle and using an irq_fwspec to use the hierarchical irqdomain API.

Make it visible to the rest of the kernel, including modules.

Link: https://lore.kernel.org/r/20210929163847.2807812-2-maz@kernel.orgTested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Host crashes when pci_enable_atomic_ops_to_root() is called for VFs with
virtual buses. The virtual buses added to SR-IOV have bus->self set to NULL
and host crashes due to this.

  PID: 4481   TASK: ffff89c6941b0000  CPU: 53  COMMAND: "bash"
  ...
   #3 [ffff9a9481713808] oops_end at ffffffffb9025cd6
   #4 [ffff9a9481713828] page_fault_oops at ffffffffb906e417
   #5 [ffff9a9481713888] exc_page_fault at ffffffffb9a0ad14
   #6 [ffff9a94817138b0] asm_exc_page_fault at ffffffffb9c00ace
      [exception RIP: pcie_capability_read_dword+28]
      RIP: ffffffffb952fd5c  RSP: ffff9a9481713960  RFLAGS: 00010246
      RAX: 0000000000000001  RBX: ffff89c6b1096000  RCX: 0000000000000000
      RDX: ffff9a9481713990  RSI: 0000000000000024  RDI: 0000000000000000
      RBP: 0000000000000080   R8: 0000000000000008   R9: ffff89c64341a2f8
      R10: 0000000000000002  R11: 0000000000000000  R12: ffff89c648bab000
      R13: 0000000000000000  R14: 0000000000000000  R15: ffff89c648bab0c8
      ORIG_RAX: ffffffffffffffff  CS: 0010  SS: 0018
   #7 [ffff9a9481713988] pci_enable_atomic_ops_to_root at ffffffffb95359a6
   #8 [ffff9a94817139c0] bnxt_qplib_determine_atomics at ffffffffc08c1a33 [bnxt_re]
   #9 [ffff9a94817139d0] bnxt_re_dev_init at ffffffffc08ba2d1 [bnxt_re]

Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit in Device
Control 2 is reserved for VFs.  The PF value applies to all associated VFs.

Return -EINVAL if pci_enable_atomic_ops_to_root() is called for a VF.

Link: https://lore.kernel.org/r/1631354585-16597-1-git-send-email-selvin.xavier@broadcom.com
Fixes: 35f5ace5 ("RDMA/bnxt_re: Enable global atomic ops if platform supports")
Fixes: 430a2368 ("PCI: Add pci_enable_atomic_ops_to_root()")
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Gospodarek <gospo@broadcom.com>

We already include <linux/device.h> and <linux/msi.h>, which
include <asm/device.h> and <asm/msi.h>.

Drop the redundant includes of <asm/device.h> and <asm/msi.h>.

[bhelgaas: squash in fix from Wan Jiabing <wanjiabing@vivo.com>:
https://lore.kernel.org/r/20211104063720.29375-1-wanjiabing@vivo.com]
Link: https://lore.kernel.org/r/20211013003145.1107148-1-kw@linux.comSigned-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev>

When cdns_plat_pcie_probe() succeeds, return success instead of falling
into the error handling code.

Fixes: bd22885a ("PCI: cadence: Refactor driver to use as a core library")
Link: https://lore.kernel.org/r/DM6PR19MB40271B93057D949310F0B0EDA0BF9@DM6PR19MB4027.namprd19.prod.outlook.comSigned-off-by: Xuliang Zhang <xlzhanga@ambarella.com>
Signed-off-by: Li Chen <lchen@ambarella.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org

If an error occurs after a successful cdns_pcie_init_phy() call, it must be
undone by a cdns_pcie_disable_phy() call, as already done above and below.

Update the goto to branch at the correct place of the error handling path.

Link: https://lore.kernel.org/r/db477b0cb444891a17c4bb424467667dc30d0bab.1624794264.git.christophe.jaillet@wanadoo.fr
Fixes: 49e0efdc ("PCI: j721e: Add support to provide refclk to PCIe connector")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>

Use the preferred generic header file linux/io.h that already includes the
corresponding asm/io.h file.

Link: https://lore.kernel.org/r/20211013003145.1107148-2-kw@linux.comSigned-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev>

This register is exported at address offset 0x30.

Link: https://lore.kernel.org/r/20211028185659.20329-8-kabel@kernel.org
Fixes: 8a3ebd8d ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org

Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG.

Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL
register on emulated bridge.

With this, the function pci_reset_secondary_bus() starts working and can
reset connected PCIe card. Custom userspace script [1] which uses setpci
can trigger PCIe Hot Reset and reset the card manually.

[1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux

Link: https://lore.kernel.org/r/20211028185659.20329-7-kabel@kernel.org
Fixes: 8a3ebd8d ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org

Aardvark controller has something like config space of a Root Port
available at offset 0x0 of internal registers - these registers are used
for implementation of the emulated bridge.

The default value of Class Code of this bridge corresponds to a RAID Mass
storage controller, though. (This is probably intended for when the
controller is used as Endpoint.)

Change the Class Code to correspond to a PCI Bridge.

Add comment explaining this change.

Link: https://lore.kernel.org/r/20211028185659.20329-6-kabel@kernel.org
Fixes: 8a3ebd8d ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org

From very vague, ambiguous and incomplete information from Marvell we
deduced that the 32-bit Aardvark register at address 0x4
(PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode
in the Functional Specification (only for Endpoint mode), controls two
16-bit PCIe registers: Command Register and Status Registers of PCIe Root
Port.

This means that bit 2 controls bus mastering and forwarding of memory and
I/O requests in the upstream direction. According to PCI specifications
bits [0:2] of Command Register, this should be by default disabled on
reset. So explicitly disable these bits at early setup of the Aardvark
driver.

Remove code which unconditionally enables all 3 bits and let kernel code
(via pci_set_master() function) to handle bus mastering of Root PCIe
Bridge via emulated PCI_COMMAND on emulated bridge.

Link: https://lore.kernel.org/r/20211028185659.20329-5-kabel@kernel.org
Fixes: 8a3ebd8d ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org # b2a56469 ("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access")

The PCIE_MSI_PAYLOAD_REG contains 16-bit MSI number, not only lower
8 bits. Fix reading content of this register and add a comment
describing the access to this register.

Link: https://lore.kernel.org/r/20211028185659.20329-4-kabel@kernel.org
Fixes: 8c39d710 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org

MSI domain callback .alloc() (implemented by advk_msi_irq_domain_alloc()
function) should return zero on success, since non-zero value indicates
failure.

When the driver was converted to generic MSI API in commit f21a8b1b
("PCI: aardvark: Move to MSI handling using generic MSI support"), it
was converted so that it returns hwirq number.

Fix this.

Link: https://lore.kernel.org/r/20211028185659.20329-3-kabel@kernel.org
Fixes: f21a8b1b ("PCI: aardvark: Move to MSI handling using generic MSI support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org

The pci_bridge_emul_conf_write() function correctly clears W1C bits in
cfgspace cache, but it does not inform the underlying implementation
about the clear request: the .write_op() method is given the value with
these bits cleared.

This is wrong if the .write_op() needs to know which bits were requested
to be cleared.

Fix the value to be passed into the .write_op() method to have requested
W1C bits set, so that it can clear them.

Both pci-bridge-emul users (mvebu and aardvark) are compatible with this
change.

Link: https://lore.kernel.org/r/20211028185659.20329-2-kabel@kernel.org
Fixes: 23a5fba4 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Cc: Russell King <rmk+kernel@armlinux.org.uk>

Update the following information related to the PCI subsystem which
includes the PCI drivers, PCI native host bridge and endpoint drivers,
and the PCI endpoint sub-system:

 - Sort fields as per preferred order
 - Sort files in the alphabetical order
 - Update old Patchwork URLs
 - Update Git repository for the PCI endpoint subsystem
 - Add Bugzilla link
 - Add link to the official IRC channel
 - Add files "drivers/pci/pci-bridge-emul.{c,h}" to the right
   section so that proper ownership is returned for both files
   from the get_maintainer.pl script

Link: https://lore.kernel.org/r/20211027105041.24087-1-kw@linux.comSigned-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>