- 08 Feb, 2023 8 commits
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Hans de Goede authored
Remove CONFI_BACKLIGHT_CLASS_DEVICE ifdef that was accidently introduced back. Reviewed-by:
Hamza Mahfooz <Hamza.Mahfooz@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored
[why] dc_link contains over 30k line of code, the decision is to break it down to files residing in link folder based on functionality. This change is the last break down change which will remove dc_link.c file after everything is broken down. [how] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why && How] Add support to read manufacturer OUI and device id from HDMI SCDC. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Fix the null pointer dererefence error when rotating the monitor on a DCN32 variant, which causes a call trace like: [ 42.469548] RIP: 0010:dcn20_program_front_end_for_ctx.cold+0x68/0x435 [amdgpu] [ 42.477140] Code: c1 4c 01 e8 48 8b b0 f0 01 00 00 e8 b6 1c 4c f9 42 f6 84 2b a0 0a 00 00 02 74 30 4d 03 ac 24 68 04 00 00 49 8b 85 f0 01 00 00 <83> b8 50 06 00 00 02 75 18 49 8b bd e0 02 00 00 48 8b 07 48 8b 40 [ 42.496225] RSP: 0018:ffffaf744326f6a0 EFLAGS: 00010282 [ 42.501539] RAX: 0000000000000000 RBX: ffff948765180000 RCX: 0000000000000000 [ 42.508797] RDX: 0000000000000000 RSI: ffffffffbaea5329 RDI: 00000000ffffffff [ 42.516055] RBP: ffff948701674400 R08: 0000000000000000 R09: ffffaf744326f538 [ 42.523312] R10: 0000000000000003 R11: ffff948a1d33ffe8 R12: ffff948708700000 [ 42.530569] R13: ffff94876e901180 R14: 0000000000000002 R15: 0000000000000001 [ 42.537825] FS: 00007f1c7c04a5c0(0000) GS:ffff948a05a80000(0000) knlGS:0000000000000000 [ 42.546055] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 42.551898] CR2: 0000000000000650 CR3: 0000000127dd6000 CR4: 00000000003506e0 [ 42.559155] Call Trace: [ 42.561645] <TASK> [ 42.563782] commit_planes_for_stream+0x8b1/0x1410 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.573298] dc_update_planes_and_stream+0x3f9/0x9f0 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.582986] amdgpu_dm_atomic_commit_tail+0x19be/0x3270 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.592944] ? vsnprintf+0x35e/0x550 [ 42.596593] commit_tail+0x94/0x130 [ 42.600146] drm_atomic_helper_commit+0x112/0x140 [ 42.604931] drm_atomic_commit+0x96/0xc0 [ 42.608922] ? drm_plane_get_damage_clips.cold+0x1c/0x1c [ 42.614326] drm_mode_atomic_ioctl+0x97b/0xb90 [ 42.618848] ? drm_atomic_set_property+0xb40/0xb40 [ 42.623633] drm_ioctl_kernel+0xc9/0x170 [ 42.627694] drm_ioctl+0x22f/0x410 [ 42.631157] ? drm_atomic_set_property+0xb40/0xb40 [ 42.636031] amdgpu_drm_ioctl+0x4a/0x80 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.644537] __x64_sys_ioctl+0x90/0xd0 [ 42.648355] do_syscall_64+0x5b/0x80 [ 42.651992] ? do_syscall_64+0x67/0x80 [ 42.655808] ? exit_to_user_mode_prepare+0x1e/0x140 [ 42.660773] entry_SYSCALL_64_after_hwframe+0x63/0xcd [ 42.665913] RIP: 0033:0x7f1c7f31aaff [ 42.669550] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00 [ 42.688635] RSP: 002b:00007fff29eca1a0 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 42.696334] RAX: ffffffffffffffda RBX: 00007fff29eca250 RCX: 00007f1c7f31aaff [ 42.703591] RDX: 00007fff29eca250 RSI: 00000000c03864bc RDI: 0000000000000009 [ 42.710848] RBP: 00000000c03864bc R08: 000000000000000e R09: 000000000000000e [ 42.718104] R10: 0000000000000007 R11: 0000000000000246 R12: 00005643f0991d70 [ 42.725361] R13: 0000000000000009 R14: 00005643f22d0c50 R15: 00005643f0a74550 [ 42.732621] </TASK> Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] DRR and Pipe cannot be updated on the same frame, or else underflow will occur. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Defer all DPP adjustment requests till optimized_required is false. Reviewed-by:
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Hamza Mahfooz authored
Currently, it is likely that we will read the relevant LTTPR caps after link training has completed (which can cause garbage data to be read), however according to the DP 2.0 spec that should be done before link training has commenced. So, instead of reading the registers on demand, use the values provided to us by DC. Reviewed-by:
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Kenneth Feng authored
enable athub cg on gc 11.0.3 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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- 03 Feb, 2023 12 commits
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Alex Deucher authored
This reverts commit 9aa15370. This is fixed now so we can re-enable S/G display on DCN 3.1.4. Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 1a65327a. This should be resolved so we can re-enable this. Also, the AGP apeture was bring programmed to 0 on MMHUB 3.0.1 since agp_start and end were not being set. Acked-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Alex Deucher authored
Take into account whether or not the AGP aperture is enabled or not when calculating the system aperture. Fixes white screens with DCN 3.1.4. Based on a patch from Yifan Zhang <yifan1.zhang@amd.com> Cc: Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2352 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Reviewed-by:
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2352 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Reviewed-by:
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Yifan Zha authored
[Why] Accessing GRBM_GFX_CNTL in full access time has risk when VF is doing MMIO attacking. Therefore, VF writing GRBM_GFX_CNTL are blocked by L1 Policy. For RLCG interface, RLCG use SCRATCH_REG2 which is copied from GRBM_GFX_CNTL. [How] Remove writing GRBM_GFX_CNTL in amdgpu_virt_rlcg_reg_rw. v2: Remove directly writing GRBM_GFX_INDEX in amdgpu_virt_rlcg_reg_rw as RLCG interface no need to use it. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Vitaly Prosyak authored
We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring a lock in drm_dev_enter during driver unload because we must call drm_dev_unplug as the beginning of unload driver sequence. Added WARNING if other PSP messages are sent without a lock. After this commit, the following commands would work -sudo modprobe -r amdgpu -sudo modprobe amdgpu Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Guilherme G. Piccoli authored
This is a very trivial code clean-up related to commit 5468c36d ("drm/amd/display: Filter Invalid 420 Modes for HDMI TMDS"). This commit added a validation on driver probe to prevent invalid TMDS modes, but one of the fake properties (swizzle) ended-up causing a warning on driver probe; was reported here: https://gitlab.freedesktop.org/drm/amd/-/issues/2264. It was fixed by commit a1cbe691 ("drm/amd/display: patch cases with unknown plane state to prevent warning"), but the validation code had a double variable assignment, which we hereby remove. Also, the fix relies in the dcn2{0,1}patch_unknown_plane_state() callbacks, so while at it we took the opportunity to perform a small code clean-up in such routines. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Mark Broadworth <mark.broadworth@amd.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Sung Joon Kim <Sungjoon.Kim@amd.com> Cc: Swapnil Patel <Swapnil.Patel@amd.com> Reviewed-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Tom Rix authored
cppcheck reports drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1403:76: style: Expression is always true because 'else if' condition is opposite to previous condition at line 1396. [multiCondition] } else if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { ^ drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1396:69: note: first condition if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { ^ drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1403:76: note: else if condition is opposite to first condition } else if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { It is not necessary to explicitly the check != condition, an else is simplier. Fixes: 238debca ("drm/amd/display: Use DML for MALL SS and Subvp allocation calculations") Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Tom Rix authored
checkpatch reports drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2902:13: style: Expression is always true because 'else if' condition is opposite to previous condition at line 2895. [multiCondition] } else if (blank) { ^ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2895:6: note: first condition if (!blank) { ^ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2902:13: note: else if condition is opposite to first condition } else if (blank) { It is not necessary to explicitly the check != condition, an else is simplier. Fixes: aa5a5777 ("drm/amd/display: Vari-bright looks disabled near end of MM14") Signed-off-by: -
ye xingchen authored
opp.h is included more than once. Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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Jonathan Neuschäfer authored
Spell it as "broadcast". Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by:
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- 31 Jan, 2023 20 commits
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Alex Deucher authored
There could be boards with DCN listed in IP discovery, but no display hardware actually wired up. In this case the vbios display table will not be populated. Detect this case and skip loading DM when we detect it. v2: Mark DCN as harvested as well so other display checks elsewhere in the driver are handled properly. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Yiqing Yao authored
These sysfs nodes are tested supported, so enable them. Signed-off-by:
Yiqing Yao <yiqing.yao@amd.com> Reviewed-by:
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Mario Limonciello authored
A mistake has been made on some boards with NBIO 4.3.0 where some NBIO registers aren't properly set by the hardware. Ensure that they're set during initialization. Cc: Natikar Basavaraj <Basavaraj.Natikar@amd.com> Tested-by:
Satyanarayana ReddyTVN <Satyanarayana.ReddyTVN@amd.com> Tested-by:
Rutvij Gajjar <Rutvij.Gajjar@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Evan Quan authored
Enable HDP clock gating control for gfx 11.0.3. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Tim Huang authored
PMFW will handle the features disablement properly for gpu reset case, driver involvement may cause some unexpected issues. Cc: stable@vger.kernel.org # 6.1 Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - fix linux dp link lost handled only one time - Reset DMUB mailbox SW state after HW reset - Unassign does_plane_fit_in_mall function from dcn3.2 - Add Function delaration in dc_link - Fix crash when connecting 2 displays with video playback - Adjust downscaling limits for dcn314 - fix FCLK pstate change underflow - Fix only one ABM pipe enabled under ODM combined case - Add missing brackets in calculation - Correct bw_params population - Fix Z8 support configurations - Add Debug Log for MST and PCON - fix MALL size hardcoded for DCN321 - add rc_params_override option in dc_dsc_config - Enable Freesync over PCon Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Hersen Wu authored
[Why] linux amdgpu defer handle link lost irq. dm add handle request to irq work queue for the first irq of link lost. if link training fails for link lost handle, link will not be enabled anymore. [How] allow adding handle request of link lost to work queue before running dp link training for link lost. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Otherwise we can be out of sync with what's in the hardware, leading to us rerunning every command that's presently in the ringbuffer. [How] Reset software state for the mailboxes in hw_reset callback. This is already done as part of the mailbox init in hw_init, but we do need to remember to reset the last cached wptr value as well here. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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George Shen authored
[Why] The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics. Using it with dcn3.2 can result in undefined behaviour. [How] Assign the function pointer to NULL. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Mustapha Ghaddar authored
[WHY] Housekeeping cleaning and adding declaration for function to be called from DM layer [HOW] Adding public functions to dc_link.h Reviewed-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Aric Cyr authored
This reverts commit 7cf5ceb3. Acked-by:
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Daniel Miess authored
[Why] Lower max_downscale_ratio and ARGB888 downscale factor to prevent cases where underflow may occur on dcn314 [How] Set max_downscale_ratio to 400 and ARGB downscale factor to 250 for dcn314 Reviewed-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Vladimir Stempen authored
[Why] Currently we set FCLK p-state change watermark calculated based on dummy p-state latency when UCLK p-state is not supported [How] Calculate FCLK p-state change watermark based on on FCLK pstate change latency in case UCLK p-state is not supported Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by:
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Leon Huang authored
[Why] ABM set pipe before updating ODM status, it leads to incorrect ABM pipe setting when enabling ODM combine. [How] Call ABM set pipe flow after ODM status update in program pipe sequence. Reviewed-by:
Chun-Liang Chang <Chun-Liang.Chang@amd.com> Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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Daniel Miess authored
[Why] Brackets missing in the calculation for MIN_DST_Y_NEXT_START [How] Add missing brackets for this calculation Reviewed-by:
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Daniel Miess authored
[Why] Underflow observed during P010 video playback on dcn314 due to incorrectly populated bw_params [How] Populate fclk, memclk and voltage in bw_params with values from max pstate rather than min pstate Reviewed-by:
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Nicholas Kazlauskas authored
[Why] It's not supported in multi-display, but it is supported in 2nd eDP screen only. [How] Remove multi display support, restrict number of planes for all z-states support, but still allow Z8 if we're not using PWRSEQ0. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Fangzhi Zuo authored
Add log for MST/PCON specific use case: 1. If DP1.2 hub where gives reduced link bw and no dsc support. 2. If less than 4-lane configuration where gives reduced bw. 3. If FRL PCON enabled for asic. 4. Track MST sink count. Reviewed-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by:
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Samson Tam authored
[Why] MALL size available can vary for different SKUs MALL size was still hardcoded for DCN321 [How] Remove hardcoding MALL size for DCN321 Reviewed-by:
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Wenjing Liu authored
[why] Current RC params are based on VESA recommended configurations. Some DSC sink may prefer non standard rc params values due to hardware limitations. To support those DSC sink we will allow DM to optionally pass rc_params_ovrd in dc_dsc_config so DC will override the default VESA recommended configurations. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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