- 11 Feb, 2020 10 commits
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Rodrigo Siqueira authored
Several modern displays support HDR/OLED panel, and one of the interesting changes provided by this technology is the new approach for handling backlight. More precisely, in the traditional way, we use PWM to manage display backlight; however, with HDR/OLED we begin to use DP Aux channel for adjusting the backlight. This patch, enable the backlight control in HDR/OLED display via DP Aux. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
Introduce vendor-specific registers for handling backlight via AUX. Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Wyatt Wood authored
[Why] Set version is currently not called. [How] Add call to set version from copy settings. This should be the only time this is called as the eDP caps should never change. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Calvin Hou authored
[WHY] Vendor dongle requires propietary OUI and handshake sequence. [HOW] Add a new structure to dc_init_data, to allow creator to pass an override vendor_oui. This value will be written to DP_SOURCE_OUI instead of AMD signature, when dpcd_set_source_specific_data is called. Signed-off-by:
Calvin Hou <Calvin.Hou@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Wyatt Wood authored
[Why] Taking up unnecessary space. [How] Remove unused values from psr struct. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] With the fallback case in place for command table offloading via DMCUB it's no longer an error for the command table to be missing specific entries. [How] Drop the BREAK_TO_DEBUGGER(); Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Martin Leung authored
[why] before we exit early in edp_reciever_ready if we detect that panel is not edp or below rev 1.2. This will skip the backlight/t7 delay panel patch. [how] edit logic to ensure panel patch is applied regardless of edp rev. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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James Zhu authored
Fix warning during switching to dpg pause mode for VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16 Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Guchun Chen authored
GDS clear workaround will cause gfx failure in suspend/resume case. [ 98.679559] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR* late_init of IP block <gfx_v9_0> failed -110 [ 98.679561] PM: dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -110 [ 98.679562] PM: Device 0000:03:00.0 failed to resume async: error -110 As this workaround is specific to the HW bug of GDS's ECC error existing in cold boot up, so bypass this workaround in suspend/ resume case after booting up. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jack Zhang authored
With the recent patch to unify VRAM address for driver table(a83f82e). VF cannot dump table info any more because SMU_MSG_SetDriverDramAddrHigh/Low were deleted in the function of smu_update_table. Therefore, VF also needs to set driver_table address in smu_hw_init to fix this regression issue. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
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- 07 Feb, 2020 9 commits
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Christian König authored
Make use of the better performance here as well. This patch is only compile tested! v2: fix calculation bug pointed out by Felix Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by:
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Christian König authored
This speeds up the access quite a bit from 2.2 MB/s to 2.9 MB/s on 32bit and 12,8 MB/s on 64bit. Signed-off-by:
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Christian König authored
This should speed up debugging VRAM access a lot. v2: add HDP flush/invalidate Signed-off-by:
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Christian König authored
Only write the _HI register when necessary. Signed-off-by:
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Jonathan Kim authored
hwc->conf was designated specifically for AMD APU IOMMU purposes. This could cause problems in performance and/or function since APU IOMMU implementation is elsewhere. Also hwc->conf and hwc->config are different members of an anonymous union so hwc->conf aliases as hw->last_tag. Signed-off-by:
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Daniel Kolesa authored
On PowerPC, the compiler will tag object files with whether they use hard or soft float FP ABI and whether they use 64 or 128-bit long double ABI. On systems with 64-bit long double ABI, a tag will get emitted whenever a double is used, as on those systems a long double is the same as a double. This will prevent linkage as other files are being compiled with hard-float. On ppc64, this code will never actually get used for the time being, as the only currently existing hardware using it are the Renoir APUs. Therefore, until this is testable and can be fixed properly, at least make sure the build will not fail. Signed-off-by:
Daniel Kolesa <daniel@octaforge.org> Signed-off-by:
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James Zhu authored
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by:
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Evan Quan authored
SMU FW will handle the features disablement for baco reset on Arcturus. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Jack Zhang authored
For sriov and pp_onevf_mode, do not send message to set smu status, because smu doesn't support these messages under VF. Besides, it should skip smu_suspend when pp_onevf_mode is disabled. Signed-off-by:
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- 06 Feb, 2020 21 commits
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Takashi Iwai authored
Currently, gcc spews a warning as: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubbub.c: In function ‘hubbub1_verify_allow_pstate_change_high’: ./include/drm/drm_print.h:316:2: warning: ‘debug_data’ may be used uninitialized in this function [-Wmaybe-uninitialized] This is because the code checks against a static value although it's basically a constant and guaranteed to be set. This patch changes the type prefix from static to const for addressing the compile warning above and also for letting the compiler optimize better. Fixes: 62d591a8 ("drm/amd/display: create new files for hubbub functions") Reviewed-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Amber Lin authored
Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc. The format is /sys/class/kfd/kfd/proc/<pid>/queues/<queue id>/XX where XX are size, type, and gpuid three files to represent queue size, queue type, and the GPU this queue uses. <queue id> folder and files underneath are generated when a queue is created. They are removed when the queue is destroyed. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
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Joseph Gravenor authored
[why] not turning off the mst hub before detection on reboot causes us to not be able to light up displays with mst hook [how] on hw init, see if any displays are lit up. if so, turn them off Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Isabel Zhang authored
[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
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Tony Cheng authored
[Why] these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern. [How] there is a driver bug where we don't check for 0, which is uninitialzed HW default. since 0 is smaller than any value we need to program, driver end up with not programming these registers Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Hersen Wu authored
[Why] old panel has been enabled for window driver but not linux. [How] enable oled panel support for linux. this patch is dc part. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Jing Zhou authored
[why] Resume from modern standby, edp stream disabled but abm keep enabled. External monitor select OTG source 0 which ABM enabled. [how] Disable abm before disable crtc when reset path mode not call core link disable stream. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The DMUB tracebuffer is useful for understanding DMCUB execution state. [How] Add a "show" attribute debugfs so we can loop through the buffer and print the entries. The structs for the entry format are defined in the debugfs since the tracebuffer header no longer exists in the DMUB service. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] Underflow is observed when plug in a 4K@60 monitor with 1366x768 eDP due to DPPCLK is too low. [How] Limit minimum DPPCLK to 100MHz. Signed-off-by:
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David Galiffi authored
[WHY] enum dc_log_type has more than 32 entries. User cannot set larger entries, like LOG_DSC. Logs from LOG_GAMMA_DEBUG where being printed even though flag was not enabled, because dal_logger_should_log check erroneously passed. [HOW] Change struct dal_logger.mask and struct dc_init_data.mask to uint64_t. Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Sung Lee authored
[WHY & HOW] Having watermark ranges saved inside clk_mgr to be available for debug at all times would be useful. Add it to the clk_mgr_internal struct for reference. Only populated for Renoir, unused for other asics. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] hyperV flag should be passed from dm to DC, and override the nv12 flip workaround flag. [How] Add flag to phy address config struct and pass the value in dm. Signed-off-by:
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Eric Yang authored
[Why] Previous logic is only good for 15W parts. Other configuration need a smarter logic to match clk levels with pp table in the fuse. [How] Cache all 8 DPM level's clock data, find lvl that match each pstate in the pp table and build input into DML base on that Signed-off-by:
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Wenjing Liu authored
[why] hwss should not guess what type of pipe lock is needed. The caller of the lock function should know the right type of pipe lock. Decouple the setup of global lock outside of pipe control lock logic. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] Engine can be NULL in some cases, so we must not acquire it. [How] Check for NULL engine before acquiring. Signed-off-by:
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Sung Lee authored
[WHY & HOW] Previously drain clk was unconstrained and fill clk was constrained on fclk. We want to change it to fill clk unconstrained and drain clock constrained to dcfclk. Signed-off-by:
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Charlene Liu authored
[why] new HW engine mapping requirment use in PSP [how] report stream_enc_inst Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Peikang Zhang authored
Description for DCHUBBUB_TEST_DEBUG_DATA is changed to avoid any future confusions. Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
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Roman Li authored
[Why] The break in apply_ctx_interdependent_lock() may potentially lead to early break from the loop leaving update plane unlocked [How] Remove break Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Peikang Zhang authored
[Why] int i can go out of boundary which will cause crash [How] Fixed the maximum value of i to avoid i going out of boundary Signed-off-by:
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