- 25 Jan, 2022 40 commits
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Martin Tsai authored
[Why] Link encoders are created based on its engine ID. The position of a link encoder in an array could be null since it didn't be allocated. Current matching logic didn't consider this situation and could get null encoder. [How] To add null encoder check to make the matching logic can go to next to get a valid one. Tested-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Martin Tsai <martin.tsai@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] Currently, when we're tentatively detecting link configuration under mst case, we will wrongly notify a none existing stream sink to drm layer. It's due to we'll call amdgpu_dm_update_connector_after_detect() within dm_helpers_read_local_edid() to update connector when we're still under tentative detection procedure. [How] dm_helpers_read_local_edid() was designed to do "read" only. Don't update drm connector status when we're still under detection process. Tested-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] There is a recent refactor that contains a typo to cause set throttled vcp size skipped for dpia link. The change is to fix this typo so it won't cause black screen Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] This is internal to dc so we don't have to add a prefix to indicate it is dc link_hwss instead someone else link_hwss. Tested-by:
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Wenjing Liu authored
[why] as we add more link_hwss we are making a generic way to determine which type of link_hwss we should use. Later on we may think of introduce a link policy layer. it could be a thin layer that decide the type of link_hwss we use. So instead of passing in link and link_res we can just pass in link_policy and swtich based on link_policy->get_link_hwss_type. Tested-by:
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Wenjing Liu authored
[why] Current we have hundreds of if/else or switch statement to check encoder type in dc_link level. The reason is because depending on the type of encoder dc_link needs to perform similar programming task but with different encoder interfaces. The story is to abstract these interfaces so dc_link can just perform the programming task without knowing the detail of which encoder it's dealing with. Tested-by:
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Wenjing Liu authored
[Why & How] DCN guard is not necessary for DP2.x relevant logic. Drop them. v2: squash in fix for misplaced #endif (Alex) Tested-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
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Jimmy Kizito authored
[Why] According to the USB4 specification, FEC and DSC should be disabled when a USB4 DPIA operates in TBT3 compatibility mode. [How] Upon detecting that a USB4 DPIA is connected to a device that is known to operate in TBT3 mode, disable FEC and DSC support if they have been reported by the TBT3 device. Tested-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] dc_link_detect_helper has multiple purpose: 1. Detect link and local sink. 2. Verify link capability by performing detection link training. 3. Start mst topology discovery and if succeeded fails the current interface. This is difficult to maintain as item 2 has become more destructive to current dc state. The change is to decouple these sequences to its own functions. Eventually only item 2 is a destructive method and we will redesign this sequence with a more unified policy across different encoder types. Tested-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Lang Yu authored
Remove redundant code and use general smu_v11_0_fini_smc_tables function. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Lang Yu authored
Some clients(e.g., kfd) query sclk/mclk through this function. As cyan skillfish doesn't support dpm, for sclk, set min/max to CYAN_SKILLFISH_SCLK_MIN/CYAN_SKILLFISH_SCLK_MAX(to maintain the existing logic).For others, set both min and max to current value. Before this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 0Mhz After this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 2000Mhz v2: - Maintain the existing min/max sclk logic.(Lijo) v3: - Avoid fetching metrics table twice.(Lijo) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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yipechai authored
This reverts commit df4f0041. Xgmi ras initialization had been moved from .late_init to early_init, the defect of repeated calling amdgpu_ras_register_ras_block had been fixed, so revert this patch. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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yipechai authored
Move xgmi ras initialization from .late_init to .early_init, which let xgmi ras can be initialized only once. Signed-off-by:
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Stanley.Yang authored
Pmfw read ecc info registers in the following order, umc0: ch_inst 0, 1, 2 ... 7 umc1: ch_inst 0, 1, 2 ... 7 The position of the register value stored in eccinfo table is calculated according to the below formula, channel_index = umc_inst * channel_in_umc + ch_inst Driver directly use the index of eccinfo table array as channel index, it's not correct, driver needs convert eccinfo table array index to channel index according to channel_idx_tbl. Reviewed-by:Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Hawking Zhang authored
create a common helper function for soc15 and onwards to read bios image from rom Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
Not needed anymore. Signed-off-by:
Zhou, Peng Ju <PengJu.Zhou@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Hawking Zhang authored
Instead of ip specific implementation for rlcg indirect register access Signed-off-by:
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Hawking Zhang authored
The helper will be used to access registers from sriov guest in full access time Signed-off-by:
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Hawking Zhang authored
Initialize all the register offsets that will be used in rlcg indirect reg access path for gfx10 in sw_init phase Signed-off-by:
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Hawking Zhang authored
Initialize all the register offsets that will be used in rlcg indirect reg access path for gfx9 in sw_init phase Signed-off-by:
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Hawking Zhang authored
Add structures that are used to cache registers offsets for rlcg indirect reg access ctrl and flag availability of such interface Signed-off-by:
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Hawking Zhang authored
Switch to common helper to query rlcg access flag specified by sriov host driver for gfx10 Signed-off-by:
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Hawking Zhang authored
Switch to common helper to query rlcg access flag specified by sriov host driver for gfx9 Signed-off-by:
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Hawking Zhang authored
Query rlc indirect register access approach specified by sriov host driver per ip blocks Signed-off-by:
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Yang Li authored
Eliminate the follow smatch warning: drivers/gpu/drm/amd/display/dc/dml/calcs/dce_calcs.c:3415 bw_calcs() warn: inconsistent indenting Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yongzhi Liu authored
[why] Resource release is needed on the error handling path to prevent memory leak. [how] Fix this by adding kfree on the error handling path. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Yongzhi Liu <lyz_cs@pku.edu.cn> Signed-off-by:
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Jiapeng Chong authored
Clean the following coccicheck warning: ./drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c:7035:2-4: WARNING: possible condition with no effect (if == else). Reported-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Xin Xiong authored
This issue takes place in an error path in amdgpu_cs_fence_to_handle_ioctl(). When `info->in.what` falls into default case, the function simply returns -EINVAL, forgetting to decrement the reference count of a dma_fence obj, which is bumped earlier by amdgpu_cs_get_fence(). This may result in reference count leaks. Fix it by decreasing the refcount of specific object before returning the error code. Reviewed-by:
Xin Xiong <xiongx18@fudan.edu.cn> Signed-off-by:
Xin Tan <tanxin.ctf@gmail.com> Signed-off-by:
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Alex Deucher authored
Some architectures (e.g., ARM) throw an compilation error if the udelay is too long. In general udelays of longer than 2000us are not recommended on any architecture. Switch to msleep in these cases. Reviewed-by:
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Alex Deucher authored
Some architectures (e.g., ARM) have relatively low udelay limits. On most architectures, anything longer than 2000us is not recommended. Change the check to align with other similar checks in DC. Reviewed-by:
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Alex Deucher authored
Older radeon boards (r2xx-r5xx) had secondary PCI functions which we solely there for supporting multi-head on OSs with special requirements. Add them to the unsupported list as well so we don't attempt to bind to them. The driver would fail to bind to them anyway, but this does so in a cleaner way that should not confuse the user. Acked-by:
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Guchun Chen authored
In multiple GPU configuration, when failed to send a SMU message, it's hard to figure out which GPU has such problem. So it's not comfortable to user. [40190.142181] amdgpu: [powerplay] last message was failed ret is 65535 [40190.242420] amdgpu: [powerplay] failed to send message 201 ret is 65535 [40190.392763] amdgpu: [powerplay] last message was failed ret is 65535 [40190.492997] amdgpu: [powerplay] failed to send message 200 ret is 65535 [40190.743575] amdgpu: [powerplay] last message was failed ret is 65535 [40190.843812] amdgpu: [powerplay] failed to send message 282 ret is 65535 Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Guchun Chen authored
NULL pointer check has guarded it already. calltrace: amdgpu_ttm_gart_bind+0x49/0xa0 [amdgpu] amdgpu_ttm_alloc_gart+0x13f/0x180 [amdgpu] amdgpu_bo_create_reserved+0x139/0x2c0 [amdgpu] ? amdgpu_ttm_debugfs_init+0x120/0x120 [amdgpu] amdgpu_bo_create_kernel+0x17/0x80 [amdgpu] amdgpu_ttm_init+0x542/0x5e0 [amdgpu] Fixes: 1b08dfb8 ("drm/amdgpu: remove gart.ready flag") Signed-off-by:
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Rajib Mahapatra authored
[Why] During resume path, dpcd_set_source_specific_data is taking extra time when core_link_write_dpcd fails on DP_SOURCE_OUI+0x03 and DP_SOURCE_MINIMUM_HBLANK_SUPPORTED. Here,aux->transfer fails with multiple retries and consume significant amount time during S0i3 resume. [How] Not to call dpcd_set_source_specific_data during resume path when there is no oled panel connected and achieve faster resume during S0i3. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
Rajib Mahapatra <rajib.mahapatra@amd.com> Signed-off-by:
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Evan Quan authored
As all those related APIs are already well protected by adev->pm.mutex. Signed-off-by:
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Evan Quan authored
As all those related APIs are already well protected by adev->pm.mutex. Signed-off-by:
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Evan Quan authored
As those APIs related are already well protected by adev->pm.mutex. Signed-off-by:
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Evan Quan authored
As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock. Signed-off-by:
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Evan Quan authored
As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock. Signed-off-by:
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