- 28 Oct, 2019 18 commits
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Chris Wilson authored
Currently we insert a arbitration point every 128MiB during a blitter copy. At 8GiB/s, this is around 30ms. This is a little on the large side if we need to inject a high priority work, so reduced it down to 8MiB or roughly 1ms. v2: Don't forget both fill/copy. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191028203012.14566-1-chris@chris-wilson.co.uk
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Michal Wajdeczko authored
While processing CSB there is no need to look at GuC submission settings, just check if engine is configured for execlists mode. While today GuC submission is disabled it's settings are still based on modparam values that might not correctly reflect actual submission status in case of any fallback. Until that is fully fixed, use alternate method to confirm that engine really runs in execlists mode by comparing set_default_submission vfunc. v2: add other immediate use of new helper Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by:
Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by:
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Chris Wilson authored
smatch complains about drivers/gpu/drm/i915//display/intel_display.c:14403 intel_set_dp_tp_ctl_normal() error: uninitialized symbol 'conn'. because it has no way to determine that the loop must have an entry. Tell the static analysers to ignore the local, it will always be set. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191028142652.1987-2-chris@chris-wilson.co.uk
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Chris Wilson authored
Keep smatch quiet, drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu() error: uninitialized symbol 'ret'. drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1280 __igt_ctx_sseu() error: uninitialized symbol 'ret'. Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:255 live_heartbeat_fast() error: uninitialized symbol 'err'. drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:320 live_heartbeat_off() error: uninitialized symbol 'err'. Signed-off-by:
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Chris Wilson authored
The request's timeline will only contain requests from this context, in order of execution. Therefore, we can simply look back along this timeline to find the currently executing request. If we do find that the current context has completed its last request, that does not imply that all requests are completed in the context, so only advance the ring->head up to the end of the known completions! Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191028124125.25176-1-chris@chris-wilson.co.uk
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Chris Wilson authored
As we use hard coded offsets for a few locations within the context image, include those in the selftests to assert that they are valid. Signed-off-by:
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Matt Roper authored
We're currently only processing AUX interrupts on the combo ports; make sure we handle the TC ports as well. v2: Drop stale comment Fixes: f663769a ("drm/i915/tgl: initialize TC and TBT ports") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024173023.22113-1-matthew.d.roper@intel.com
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Chris Wilson authored
Iterate over all user-accessible render engines when checking whether they can be adjusted for sseu. Signed-off-by:
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Chris Wilson authored
Use any blitter engine at random for prefilling the memory region. Signed-off-by:
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Chris Wilson authored
Since the rps is tied to its intel_gt, use that backpointer to find the right engine rather than delving into i915. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191027175505.25470-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Select a random user accessible engine for checking coherency results. While we should check all engines, we use a random selection so that over repeated runs we cover all. Signed-off-by:
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Jani Nikula authored
Add definition for block 56, the compression parameters. v2: add missing slice_height (Vandita) Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024075608.11511-1-jani.nikula@intel.com
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Chris Wilson authored
Check all user accessible engines that can blit work with our blitter client. Signed-off-by:
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Chris Wilson authored
As we are inside the gt, we have a local gt->engine[] lookup we should be using in preference over the i915->engine[] copy. Signed-off-by:
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Chris Wilson authored
We need to verify that our blitter routines perform as expected, so measure it. Signed-off-by:
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Ville Syrjälä authored
Add CHICKEN_TRANS definition for transcoder D. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024122138.25065-2-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
Make CHICKEN_TRANS() a bit less special looking by using _PICK(). Signed-off-by:
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- 27 Oct, 2019 2 commits
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Chris Wilson authored
ips uses clock delays as opposed to rps frequency bins. To fit the delays into the same rps calculations, we need to invert the ips delays. Fixes: 3e7abf81 ("drm/i915: Extract GT render power state management") Signed-off-by:
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Chris Wilson authored
We would like some freedom to break the user API/ABI for future HW but yet still expose the driver for upstream development on that HW. Currently, we have the i915.force_probe module parameter to avoid binding to HW while the driver is under development, but that is still a little too soft with respect to the stringent no-regression rules if we also plan to be redesigning the uAPI to go along with the new HW. To allow the uAPI to be changed during development, only expose that API and in development HW under STAGING (and BROKEN). Hopefully, making it explicit that such interfaces to that HW are under development and not to be blindly enabled by distributions. Signed-off-by:
Dave Airlie <airlied@redhat.com> Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191027154314.11139-1-chris@chris-wilson.co.uk
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- 26 Oct, 2019 5 commits
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Chris Wilson authored
Pull the memory region bookkeeping into its file. Let's start clean and see how long it lasts! Signed-off-by:
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Andi Shyti authored
Pull the GuC interrupt handlers out of i915_irq.c. They now use the GT interrupt facilities rather than the central dispatch. Based on a patch by Chris Wilson. Signed-off-by:
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Andi Shyti authored
i915_irq.c is large. One reason for this is that has a large chunk of the GT render power management stashed away in it. Extract that logic out of i915_irq.c and intel_pm.c and put it under one roof. Based on a patch by Chris Wilson. Signed-off-by:
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Chris Wilson authored
The location of RING_MI_MODE (used to stop the ring across resets) moved for Tigerlake. Fixup the new location and include a selftest to verify the location in the default context image. Signed-off-by:
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Chris Wilson authored
Avoid angering clang and smatch by using a constant value in a '&&' test, by forcing that constant value into a boolean. E.g., drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand] if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) { ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by:kbuild test robot <lkp@intel.com> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191025135943.12524-1-chris@chris-wilson.co.uk
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- 25 Oct, 2019 15 commits
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José Roberto de Souza authored
This sequence was recently added to fix internal HW sequences to reset TC ports. HSDES: 1507287614 HSDES: 14010071447 BSpec: 49292 Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Chris Wilson authored
As the GT may be running in parallel with the module initialisation code, we may enter i915_pmu_gt_parked() as we are executing i915_pmu_register(). We have to init the spinlock before we mark pmu.event_init so that it is available for use by i915_pmu_gt_parked() (which may run as soon as event_init is set). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112127Signed-off-by:
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Matthew Auld authored
We can be more aggressive in our testing by launching a number of kthreads, where each is submitting its own copy or fill batches on a set of random sized objects. Also since the underlying fill and copy batches can be pre-empted mid-batch(for particularly large objects), throw in a random mixture of ctx priorities per thread to make pre-emption a possibility. Signed-off-by:
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Matthew Auld authored
Now that for all the relevant backends we do randomised testing, we need to make sure we still sanity check the obvious cases that might blow up, such that introducing a temporary regression is less likely. Also rather than do this for every backend, just limit to our two memory types: system and local. Suggested-by:
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Matthew Auld authored
Ditch the dubious static list of sizes to enumerate, in favour of choosing a random size within the limits of each backing store. With repeated CI runs this should give us a wider range of object sizes, and in turn more page-size combinations, while using less machine time. Signed-off-by:
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Matthew Auld authored
Add LMEM objects to list of backends we test for huge-GTT-pages. Signed-off-by:
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Matthew Auld authored
Simple test writing to dwords across an object, using various engines in a randomized order, checking that our writes land from the cpu. Signed-off-by:
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Abdiel Janulgue authored
We can create LMEM objects, but we also need to support mapping them into kernel space for internal use. Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by:
Steve Hampson <steven.t.hampson@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
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Abdiel Janulgue authored
Create an io-mapping to describe the CPU aperture for lmem. Signed-off-by:
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Matthew Auld authored
We currently define LMEM, or local memory, as just another memory region, like system memory or stolen, which we can expose to userspace and can be mapped to the CPU via some BAR. Signed-off-by:
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Lucas De Marchi authored
Split gen11_irq_handler() to receive as parameter the function pointers. This allows to share the interrupt handler even if the enable/disable functions are different. Make sure it's always inlined to avoid the extra indirect call on the hot path. Checking with gcc 9 this produce the exact same code as of now: $ size drivers/gpu/drm/i915/i915_irq*.o text data bss dec hex filename 47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq.o 47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq_new.o $ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq.o' -ex 'disassemble gen11_irq_handler' > /tmp/old.s $ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq_new.o' -ex 'disassemble gen11_irq_handler' > /tmp/new.s $ git diff --no-index /tmp/{old,new}.s $ So, no change in behavior, just a simple refactor. Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: -
Lucas De Marchi authored
On dgfx there's no LLC and eDRAM control table. Since now this also means the device has global MOCS, just return early on the initialization function. L3 settings still apply and still need to be tweaked. Bspec: 45101 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024195122.22877-3-lucas.demarchi@intel.com
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Stuart Summers authored
Add a new macro for GEN12 platforms to be grouped under dgfx feature set. Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Signed-off-by:
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José Roberto de Souza authored
This will be helpful to diferentiate a set of GPUs with the same GEN version. Signed-off-by:
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Lionel Landwerlin authored
TGL introduced a feature in which we map the main surface to the auxiliary surface. If we screw up the page tables, the HW has a register to tell us which engine encounters a fault in the page table walk. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by:
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