1. 22 Jul, 2020 12 commits
  2. 17 Jul, 2020 16 commits
  3. 16 Jul, 2020 8 commits
  4. 15 Jul, 2020 1 commit
  5. 14 Jul, 2020 3 commits
    • Mark Brown's avatar
      Merge series "mtd: spi-nor: add xSPI Octal DTR support" from Pratyush Yadav <p.yadav@ti.com>: · 510a230b
      Mark Brown authored
      Hi,
      
      This series adds support for octal DTR flashes in the spi-nor framework,
      and then adds hooks for the Cypress Semper and Mircom Xcella flashes to
      allow running them in octal DTR mode. This series assumes that the flash
      is handed to the kernel in Legacy SPI mode.
      
      Tested on TI J721e EVM with 1-bit ECC on the Cypress flash.
      
      Changes in v10:
      - Rebase on latest linux-next/master. Drop a couple patches that made it
        in the  previous release.
      
      - Move the code that sets 20 dummy cycles for MT35XU512ABA to its octal
        enable function. This way, if the controller doesn't support 8D mode
        20 dummy cycles won't be used.
      
      Changes in v9:
      - Do not use '& 0xff' to get the opcode LSB in spi-mxic and
        spi-zynq-qspi. The cast to u8 will do that anyway.
      
      - Do not use if (opcode) as a check for whether the command phase exists
        in spi-zynq-qspi because the opcode 0 can be valid. Use the new
        cmd.nbytes instead.
      
      Changes in v8:
      - Move controller changes in spi-mxic to the commit which introduces
        2-byte opcodes to avoid problems when bisecting.
      
      - Replace usage of sizeof(op->cmd.opcode) with op->cmd.nbytes.
      
      - Extract opcode in spi-zynq-qspi instead of using &op->cmd.opcode.
      
      Changes in v7:
      - Reject ops with more than 1 command byte in
        spi_mem_default_supports_op().
      
      - Reject ops with more than 1 command byte in atmel and mtk controllers.
      
      - Reject ops with 0 command bytes in spi_mem_check_op().
      
      - Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD().
      
      - Avoid endianness problems in spi-mxic.
      
      Changes in v6:
      - Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find
        them out from the Profile 1.0 table.
      
      Changes in v5:
      - Do not enable stateful X-X-X modes if the reset line is broken.
      
      - Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table
        parsing, do it in spi_nor_info_init_params() instead based on the
        SPI_NOR_OCTAL_DTR_READ flag instead.
      
      - Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this
        capability is no longer set in Profile 1.0 parsing.
      
      - Instead of just checking for spi_nor_get_protocol_width() in
        spi_nor_octal_dtr_enable(), make sure the protocol is
        SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data
        width.
      
      - Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability
        via BFPT.
      
      - Do not make an invalid Quad Enable BFPT field a fatal error. Silently
        ignore it by assuming no quad enable bit is present.
      
      - Set dummy cycles for Cypress Semper flash to 24 instead of 20. This
        allows for 200MHz operation in 8D mode compared to the 166MHz with 20.
      
      - Rename spi_nor_cypress_octal_enable() to
        spi_nor_cypress_octal_dtr_enable().
      
      - Update spi-mtk-nor.c to reject DTR ops since it doesn't call
        spi_mem_default_supports_op().
      
      Changes in v4:
      - Refactor the series to use the new spi-nor framework with the
        manufacturer-specific bits separated from the core.
      
      - Add support for Micron MT35XU512ABA.
      
      - Use cmd.nbytes as the criteria of whether the data phase exists or not
        instead of cmd.buf.in || cmd.buf.out in spi_nor_spimem_setup_op().
      
      - Update Read FSR to use the same dummy cycles and address width as Read
        SR.
      
      - Fix BFPT parsing stopping too early for JESD216 rev B flashes.
      
      - Use 2 byte reads for Read SR and FSR commands in DTR mode.
      
      Changes in v3:
      - Drop the DT properties "spi-rx-dtr" and "spi-tx-dtr". Instead, if
        later a need is felt to disable DTR in case someone has a board with
        Octal DTR capable flash but does not support DTR transactions for some
        reason, a property like "spi-no-dtr" can be added.
      
      - Remove mode bits SPI_RX_DTR and SPI_TX_DTR.
      
      - Remove the Cadence Quadspi controller patch to un-block this series. I
        will submit it as a separate patch.
      
      - Rebase on latest 'master' and fix merge conflicts.
      
      - Update read and write dirmap templates to use DTR.
      
      - Rename 'is_dtr' to 'dtr'.
      
      - Make 'dtr' a bitfield.
      
      - Reject DTR ops in spi_mem_default_supports_op().
      
      - Update atmel-quadspi to reject DTR ops. All other controller drivers
        call spi_mem_default_supports_op() so they will automatically reject
        DTR ops.
      
      - Add support for both enabling and disabling DTR modes.
      
      - Perform a Software Reset on flashes that support it when shutting
        down.
      
      - Disable Octal DTR mode on suspend, and re-enable it on resume.
      
      - Drop enum 'spi_mem_cmd_ext' and make command opcode u16 instead.
        Update spi-nor to use the 2-byte command instead of the command
        extension. Since we still need a "extension type", mode that enum to
        spi-nor and name it 'spi_nor_cmd_ext'.
      
      - Default variable address width to 3 to fix SMPT parsing.
      
      - Drop non-volatile change to uniform sector mode and rely on parsing
        SMPT.
      
      Changes in v2:
      - Add DT properties "spi-rx-dtr" and "spi-tx-dtr" to allow expressing
        DTR capabilities.
      
      - Set the mode bits SPI_RX_DTR and SPI_TX_DTR when we discover the DT
        properties "spi-rx-dtr" and spi-tx-dtr".
      
      - spi_nor_cypress_octal_enable() was updating nor->params.read[] with
        the intention of setting the correct number of dummy cycles. But this
        function is called _after_ selecting the read so setting
        nor->params.read[] will have no effect. So, update nor->read_dummy
        directly.
      
      - Fix spi_nor_spimem_check_readop() and spi_nor_spimem_check_pp()
        passing nor->read_proto and nor->write_proto to
        spi_nor_spimem_setup_op() instead of read->proto and pp->proto
        respectively.
      
      - Move the call to cqspi_setup_opcode_ext() inside cqspi_enable_dtr().
        This avoids repeating the 'if (f_pdata->is_dtr)
        cqspi_setup_opcode_ext()...` snippet multiple times.
      
      - Call the default 'supports_op()' from cqspi_supports_mem_op(). This
        makes sure the buswidth requirements are also enforced along with the
        DTR requirements.
      
      - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it
        when a phase is DTR so it is redundant.
      
      Pratyush Yadav (17):
        spi: spi-mem: allow specifying whether an op is DTR or not
        spi: spi-mem: allow specifying a command's extension
        spi: atmel-quadspi: reject DTR ops
        spi: spi-mtk-nor: reject DTR ops
        mtd: spi-nor: add support for DTR protocol
        mtd: spi-nor: sfdp: get command opcode extension type from BFPT
        mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
        mtd: spi-nor: core: use dummy cycle and address width info from SFDP
        mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
        mtd: spi-nor: core: enable octal DTR mode when possible
        mtd: spi-nor: sfdp: do not make invalid quad enable fatal
        mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT
        mtd: spi-nor: core: perform a Soft Reset on shutdown
        mtd: spi-nor: core: disable Octal DTR mode on suspend.
        mtd: spi-nor: core: expose spi_nor_default_setup() in core.h
        mtd: spi-nor: spansion: add support for Cypress Semper flash
        mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode
      
       drivers/mtd/spi-nor/core.c      | 446 +++++++++++++++++++++++++++-----
       drivers/mtd/spi-nor/core.h      |  22 ++
       drivers/mtd/spi-nor/micron-st.c | 103 +++++++-
       drivers/mtd/spi-nor/sfdp.c      | 131 +++++++++-
       drivers/mtd/spi-nor/sfdp.h      |   8 +
       drivers/mtd/spi-nor/spansion.c  | 166 ++++++++++++
       drivers/spi/atmel-quadspi.c     |   6 +
       drivers/spi/spi-mem.c           |  16 +-
       drivers/spi/spi-mtk-nor.c       |  10 +-
       drivers/spi/spi-mxic.c          |   3 +-
       drivers/spi/spi-zynq-qspi.c     |  11 +-
       include/linux/mtd/spi-nor.h     |  53 +++-
       include/linux/spi/spi-mem.h     |  14 +-
       13 files changed, 889 insertions(+), 100 deletions(-)
      
      --
      2.27.0
      
      base-commit: b3a9e3b9
      
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      510a230b
    • Linus Walleij's avatar
      spi: omap-100k: Drop include · 8257083f
      Linus Walleij authored
      The OMAP-100k driver includes <linux/gpio.h> but does not
      use any symbols from it, so drop the include.
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Link: https://lore.kernel.org/r/20200714073357.34879-1-linus.walleij@linaro.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      8257083f
    • Pratyush Yadav's avatar
      spi: spi-mtk-nor: reject DTR ops · 4728f073
      Pratyush Yadav authored
      Double Transfer Rate (DTR) ops are added in spi-mem. But this controller
      doesn't support DTR transactions. Since we don't use the default
      supports_op(), which rejects all DTR ops, do that explicitly in our
      supports_op().
      Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
      Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Link: https://lore.kernel.org/r/20200623183030.26591-5-p.yadav@ti.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      4728f073