- 05 Nov, 2022 3 commits
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Johan Hovold authored
Move the device-id table below probe() and next to the driver structure to keep the driver callback functions grouped together. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221028160435.26948-4-johan+linaro@kernel.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Johan Hovold authored
Sort the device-id table by compatible string to make it easier to find and add new entries. Reviewed-by:
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Johan Hovold authored
The PCS_USB register block lives at an offset of 0x1000 from the PCS region on SC8280XP so add the missing offset to avoid corrupting unrelated registers on runtime suspend. Note that the current binding is broken as it does not describe the PCS_USB region and the PCS register size does not cover PCS_USB and the regions in between. As Linux currently maps full pages, simply adding the offset to driver works until the binding has been fixed. Fixes: c0c7769c ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy") Reviewed-by:
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- 28 Oct, 2022 37 commits
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Vinod Koul authored
Merge the fixes to next as both carry qmp-phy patches
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Johan Hovold authored
Add support for the new SC8280XP binding. Note that the binding does not try to describe every register subregion and instead the driver holds the corresponding offsets. Also note that the driver will continue to accept the old binding, at least for the time being. Signed-off-by:
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Johan Hovold authored
In preparation for supporting devicetree bindings which do not use a child node, move the PHY creation to probe() proper and parse the serdes resource in what is now the legacy devicetree helper. Signed-off-by:
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Johan Hovold authored
The current QMP UFS PHY bindings are based on the original MSM8996 PCIe PHY binding which provided multiple PHYs per IP block and these in turn were described by child nodes. The QMP UFS PHY block only provide a single PHY and the remnant child node does not really reflect the hardware. The original MSM8996 binding also ended up describing the individual register blocks as belonging to either the wrapper node or the PHY child nodes. This is an unnecessary level of detail which has lead to problems when later IP blocks using different register layouts have been forced to fit the original mould rather than updating the binding. The bindings are arguable also incomplete as they only the describe register blocks used by the current Linux drivers. Add a new binding for the UFS QMP PHYs found on SC8280XP which further bindings can be based on. Note that the current binding is simply removed instead of being deprecated as it was only recently merged and support for SC8280XP is still under development. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-9-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
The current QMP UFS PHY bindings are based on the original MSM8996 PCIe PHY binding which provided multiple PHYs per IP block and these in turn were described by child nodes. The QMP UFS PHY block only provide a single PHY and the remnant child node does not really reflect the hardware. The original MSM8996 binding also ended up describing the individual register blocks as belonging to either the wrapper node or the PHY child nodes. This is an unnecessary level of detail which has lead to problems when later IP blocks using different register layouts have been forced to fit the original mould rather than updating the binding. The bindings are arguable also incomplete as they only the describe register blocks used by the current Linux drivers. In preparation for adding new bindings for SC8280XP which further bindings can be based on, rename the current bindings after MSM8996 and add a reference to the SC8280XP bindings. Signed-off-by:
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Johan Hovold authored
Clean up the PHY initialisation somewhat programming both tx and rx for the second lane after the first lane. Signed-off-by:
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Johan Hovold authored
Rename the PHY operation structure so that it has a "phy_ops" suffix and move it next to the implementation. Signed-off-by:
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Johan Hovold authored
Stop abusing the driver data pointer and instead pass the driver state structure directly to the initialisation helpers during probe. Signed-off-by:
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Johan Hovold authored
Since the QMP driver split there will be at most a single child node so drop the obsolete iteration construct. While at it, drop the verbose error logging that would have been printed also on probe deferrals. Note that there's no need to check if there are additional child nodes (the kernel is not a devicetree validator), but let's return an error if there are no child nodes at all for now. Signed-off-by:
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Johan Hovold authored
The UFS QMP PHY driver only manages a single PHY so merge the old qcom_qmp and qmp_phy structures and drop the PHY array. Signed-off-by:
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Johan Hovold authored
Move the device-id table below probe() and next to the driver structure to keep the driver callback functions grouped together. Signed-off-by:
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Johan Hovold authored
Commit fc646236 ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region") started treating the PCS_USB registers as potentially separate from the PCS registers but used the wrong base when no PCS_USB offset has been provided. Fix the PCS_USB base used at runtime resume to prevent dereferencing a NULL pointer on platforms that do not provide a PCS_USB offset (e.g. SC7180). Fixes: fc646236 ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region") Cc: stable@vger.kernel.org # 5.20 Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20221026162116.26462-1-johan+linaro@kernel.orgSigned-off-by:
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Dmitry Baryshkov authored
According to the kernel 4.4 sources from NHSS.QSDK.9.0.2 and according to hardware docs, the PHY registers layout used for IPQ8074 USB3 PHY is incorrect. This platform uses offset 0x174 for the PCS_STATUS register, 0xd8 for PCS_AUTONOMOUS_MODE_CTRL, etc. Correct the PHY registers layout. Fixes: 94a407cc ("phy: qcom-qmp: create copies of QMP PHY driver") Fixes: 507156f5 ("phy: qcom-qmp: Add USB QMP PHY support for IPQ8074") Signed-off-by:
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Johan Hovold authored
Drop the start and pwrdn-ctrl abstractions which are no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
Drop the start and pwrdn-ctrl abstractions which are no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
Drop the start and pwrdn-ctrl abstractions which are no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
The driver expects every configuration to set the pwrdn_ctrl and phy_status masks. Add some probe WARN_ON_ONCE() to probe to catch any new driver support that fails to provide them. Signed-off-by:
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Johan Hovold authored
All PCIe PHYs need to start and stop the SerDes and PCS so drop the start-ctrl abstraction which is no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
All USB PHYs need to start and stop the SerDes and PCS so drop the start-ctrl abstraction which is no longer needed since the QMP driver split. Similarly, drop the pwrdn-ctrl abstraction which also is not needed since the split. Signed-off-by:
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Johan Hovold authored
It typically takes between one and two milliseconds for the PHY to become ready after starting it. Increase the tight 3--10 us polling period to the more reasonable 51--200 us. Signed-off-by:
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Johan Hovold authored
Clean up the PHY status polling by dropping the configuration mask which is no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
It typically takes between one and two milliseconds for the PHY to become ready after starting it. Increase the tight 3--10 us polling period to the more reasonable 51--200 us. Signed-off-by:
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Johan Hovold authored
Clean up the PHY ready polling by dropping the mask variables which are no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
Drop the unused phy-status configuration mask which has never been used for UFS PHYs. Signed-off-by:
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Johan Hovold authored
It typically takes between one and two milliseconds for the PHY to become ready after starting it. Increase the tight 3--10 us polling period to the more reasonable 51--200 us. Signed-off-by:
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Johan Hovold authored
Clean up the PHY status polling by dropping the configuration mask which is no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
It typically takes between one and two milliseconds for the PHY to become ready after starting it. Increase the tight 3--10 us polling period to the more reasonable 51--200 us. Signed-off-by:
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Johan Hovold authored
Clean up the PHY ready and status polling by dropping the configuration masks which are no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
It typically takes between one and two milliseconds for the PHY to become ready after starting it. Increase the tight 3--10 us polling period to the more reasonable 51--200 us. Signed-off-by:
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Johan Hovold authored
Clean up the status polling by dropping the ready bit mask which is no longer needed since the QMP driver split. Signed-off-by:
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Johan Hovold authored
The phy_status mask was never set for IPQ6018 which meant that the driver would not wait for the PHY to be initialised during power-on and would never detect PHY initialisation timeouts. Fixes: 520264db ("phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx") Signed-off-by:
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Johan Hovold authored
The phy_status mask was never set for IPQ8074 (gen3) which meant that the driver would not wait for the PHY to be initialised during power-on and would never detect PHY initialisation timeouts. Fixes: 334fad18 ("phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support") Signed-off-by:
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Johan Hovold authored
The phy_status mask was never set for SC8180X which meant that the driver would not wait for the PHY to be initialised during power-on and would never detect PHY initialisation timeouts. Fixes: f839f14e ("phy: qcom-qmp: Add sc8180x PCIe support") Signed-off-by:
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Vidya Sagar authored
Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change to Gen1 during initialization. This helps in the below surprise link down cases, - Surprise link down happens at Gen3/Gen4 link speed. - Surprise link down happens and external REFCLK is cut off, which causes UPHY PLL rate to deviate to an invalid rate. Signed-off-by:
Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20221013183854.21087-9-vidyas@nvidia.comSigned-off-by:
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Johan Hovold authored
The power-down delay was included in the first version of the QMP driver as an optional delay after powering on the PHY (using POWER_DOWN_CONTROL) and just before starting it. Later changes modified this sequence by powering on before initialising the PHY, but the optional delay stayed where it was (i.e. before starting the PHY). The vendor driver does not use a delay before starting the PHY and this is likely not needed on any platform unless there is a corresponding delay in the vendor kernel init sequence tables (i.e. in devicetree). Let's keep the delay for now, but drop the redundant delay period configuration while increasing the unnecessarily low timer slack somewhat. Reviewed-by:
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Johan Hovold authored
The SC8280XP PHY does not need a delay before starting the PHY (which is what the has_pwrdn_delay config option really controls) so drop the unnecessary delay. Signed-off-by:
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Johan Hovold authored
The power-down delay was included in the first version of the QMP driver as an optional delay after powering on the PHY (using POWER_DOWN_CONTROL) and just before starting it. Later changes modified this sequence by powering on before initialising the PHY, but the optional delay stayed where it was (i.e. before starting the PHY). The vendor driver does not use a delay before starting the PHY and this is likely not needed on any platform unless there is a corresponding delay in the vendor kernel init sequence tables (i.e. in devicetree). Let's keep the delay for now, but drop the redundant delay period configuration while increasing the unnecessarily low timer slack somewhat. Reviewed-by:
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