1. 01 Aug, 2018 1 commit
    • Paul Burton's avatar
      MIPS: Remove nabi_no_regargs · 96a68b14
      Paul Burton authored
      Our sigreturn functions make use of a macro named nabi_no_regargs to
      declare 8 dummy arguments to a function, forcing the compiler to expect
      a pt_regs structure on the stack rather than in argument registers. This
      is an ugly hack which unnecessarily causes these sigreturn functions to
      need to care about the calling convention of the ABI the kernel is built
      for. Although this is abstracted via nabi_no_regargs, it's still ugly &
      unnecessary.
      
      Remove nabi_no_regargs & the struct pt_regs argument from sigreturn
      functions, and instead use current_pt_regs() to find the struct pt_regs
      on the stack, which works cleanly regardless of ABI.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/20106/
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      96a68b14
  2. 31 Jul, 2018 4 commits
  3. 30 Jul, 2018 5 commits
    • Quentin Schulz's avatar
      MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller · 6386889a
      Quentin Schulz authored
      The GPIO controller also serves as an interrupt controller for events
      on the GPIO it handles.
      
      An interrupt occurs whenever a GPIO line has changed.
      Signed-off-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
      Acked-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/20015/
      Cc: robh+dt@kernel.org
      Cc: mark.rutland@arm.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: linux-gpio@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: thomas.petazzoni@bootlin.com
      6386889a
    • Paul Burton's avatar
      MIPS: generic: Select MIPS_AUTO_PFN_OFFSET · 0211d49e
      Paul Burton authored
      Enable CONFIG_MIPS_AUTO_PFN_OFFSET for the generic platform, allowing
      it to avoid wasted book-keeping for pages with addresses lower than the
      physical base address of memory.
      
      This has a minimal impact on kernel text size, with 64r6el_defconfig
      gaining 0.1% in size as reported by bloat-o-meter:
      
        add/remove: 4/1 grow/shrink: 345/13 up/down: 9017/-392 (8625)
        Function                                     old     new   delta
        pcpu_setup_first_chunk                      1444    1780    +336
        pcpu_alloc_first_chunk                       864    1136    +272
        start_kernel                                1064    1288    +224
        initcall_blacklist                           224     372    +148
        try_fill_recv                               2088    2184     +96
        ...
        Total: Before=8457273, After=8465898, chg +0.10%
      
      The gain for systems with large offsets to physical memory & the ability
      to continue using generic kernels on such systems seems well worth this
      small cost.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Suggested-by: default avatarVladimir Kondratiev <vladimir.kondratiev@intel.com>
      Patchwork: https://patchwork.linux-mips.org/patch/20049/
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      0211d49e
    • Paul Burton's avatar
      MIPS: Allow auto-dection of ARCH_PFN_OFFSET & PHYS_OFFSET · 6c359eb1
      Paul Burton authored
      On systems where physical memory begins at a non-zero address, defining
      PHYS_OFFSET (which influences ARCH_PFN_OFFSET) can save us time & memory
      by avoiding book-keeping for pages from address zero to the start of
      memory.
      
      Some MIPS platforms already make use of this, but with the definition of
      PHYS_OFFSET being compile-time constant it hasn't been possible to
      enable this optimization for a kernel which may run on systems with
      varying physical memory base addresses.
      
      Introduce a new Kconfig option CONFIG_MIPS_AUTO_PFN_OFFSET which, when
      enabled, makes ARCH_PFN_OFFSET a variable & detects it from the boot
      memory map (which for example may have been populated from DT). The
      relationship with PHYS_OFFSET is reversed, with PHYS_OFFSET now being
      based on ARCH_PFN_OFFSET. This is because ARCH_PFN_OFFSET is used far
      more often, so avoiding the need for runtime calculation gives us a
      smaller impact on kernel text size (0.1% rather than 0.15% for
      64r6el_defconfig).
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Suggested-by: default avatarVladimir Kondratiev <vladimir.kondratiev@intel.com>
      Patchwork: https://patchwork.linux-mips.org/patch/20048/
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      6c359eb1
    • Paul Burton's avatar
      MIPS: Fix ISA virt/bus conversion for non-zero PHYS_OFFSET · 0494d7ff
      Paul Burton authored
      isa_virt_to_bus() & isa_bus_to_virt() claim to treat ISA bus addresses
      as being identical to physical addresses, but they fail to do so in the
      presence of a non-zero PHYS_OFFSET.
      
      Correct this by having them use virt_to_phys() & phys_to_virt(), which
      consolidates the calculations to one place & ensures that ISA bus
      addresses do indeed match physical addresses.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/20047/
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
      0494d7ff
    • Paul Burton's avatar
      MIPS: Make (UN)CAC_ADDR() PHYS_OFFSET-agnostic · 0d0e1477
      Paul Burton authored
      Converting an address between cached & uncached (typically addresses in
      (c)kseg0 & (c)kseg1 or 2 xkphys regions) should not depend upon
      PHYS_OFFSET in any way - we're converting from a virtual address in one
      unmapped region to a virtual address in another unmapped region.
      
      For some reason our CAC_ADDR() & UNCAC_ADDR() macros make use of
      PAGE_OFFSET, which typically includes PHYS_OFFSET. This means that
      platforms with a non-zero PHYS_OFFSET typically have to workaround
      miscalculation by these 2 macros by also defining UNCAC_BASE to a value
      that isn't really correct.
      
      It appears that an attempt has previously been made to address this with
      commit 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for
      PHYS_OFFSET") which was later undone by commit ed3ce16c ("Revert
      "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"") which
      also introduced the ar7 workaround. That attempt at a fix was roughly
      equivalent, but essentially caused the CAC_ADDR() & UNCAC_ADDR() macros
      to cancel out PHYS_OFFSET by adding & then subtracting it again. In his
      revert Leonid is correct that using PHYS_OFFSET makes no sense in the
      context of these macros, but appears to have missed its inclusion via
      PAGE_OFFSET which means PHYS_OFFSET actually had an effect after the
      revert rather than before it.
      
      Here we fix this by modifying CAC_ADDR() & UNCAC_ADDR() to stop using
      PAGE_OFFSET (& thus PHYS_OFFSET), instead using __pa() & __va() along
      with UNCAC_BASE.
      
      For UNCAC_ADDR(), __pa() will convert a cached address to a physical
      address which we can simply use as an offset from UNCAC_BASE to obtain
      an address in the uncached region.
      
      For CAC_ADDR() we can undo the effect of UNCAC_ADDR() by subtracting
      UNCAC_BASE and using __va() on the result.
      
      With this change made, remove definitions of UNCAC_BASE from the ar7 &
      pic32 platforms which appear to have defined them only to workaround
      this problem.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      References: 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET")
      References: ed3ce16c ("Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"")
      Patchwork: https://patchwork.linux-mips.org/patch/20046/
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
      0d0e1477
  4. 28 Jul, 2018 4 commits
  5. 27 Jul, 2018 1 commit
    • Christoph Hellwig's avatar
      MIPS: remove mips_swiotlb_ops · a999933d
      Christoph Hellwig authored
      mips_swiotlb_ops differs from the generic swiotlb_dma_ops only in that
      it contains a mb() barrier after each operations that maps or syncs
      dma memory to the device.
      
      The dma operations are defined to not be memory barriers, but instead
      the write* operations to kick the DMA off are supposed to contain them.
      
      For mips this handled by war_io_reorder_wmb(), which evaluates to the
      stronger wmb() instead of the pure compiler barrier barrier() for
      just those platforms that use swiotlb, so I think we are covered
      properly.
      
      [paul.burton@mips.com:
        - Include linux/swiotlb.h to fix build failures for configs with
          CONFIG_SWIOTLB=y.]
      Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/20038/
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@linux-mips.org
      Cc: iommu@lists.linux-foundation.org
      Cc: linux-kernel@vger.kernel.org
      a999933d
  6. 26 Jul, 2018 5 commits
  7. 25 Jul, 2018 11 commits
  8. 24 Jul, 2018 9 commits
    • Paul Burton's avatar
      MIPS: Hardcode cpu_has_* where known at compile time due to ISA · 93e01942
      Paul Burton authored
      Many architectural features have over time moved from being optional to
      either be required or removed by newer architecture releases. This means
      that in many cases we can know at compile time whether a feature will be
      supported or not purely due to the knowledge we have about the ISA the
      kernel build is targeting.
      
      This patch introduces a bunch of utility macros for checking for
      supported options, ASEs & combinations of those with ISA revisions. It
      then makes use of these in the default definitions of cpu_has_* macros.
      The result is that many of the macros become compile-time constant,
      allowing more optimisation opportunities for the compiler - particularly
      with kernels built for later ISA revisions.
      
      To demonstrate the effect of this patch, the following table shows the
      size in bytes of the kernel binary as reported by scripts/bloat-o-meter
      for v4.12-rc4 maltasmvp_defconfig kernels with & without this patch. A
      variant of maltasmvp_defconfig with CONFIG_CPU_MIPS32_R6 selected is
      also shown, to demonstrate that MIPSr6 systems benefit more due to extra
      features becoming required by that architecture revision. Builds of
      pistachio_defconfig are also shown, as although this is a MIPSr2
      platform it doesn't hardcode any features in a machine-specific
      cpu-feature-overrides.h, which allows it to gain more from this patch
      than the equivalent Malta r2 build.
      
           Config         | Before  | After   |  Change
          ----------------|---------|---------|---------
           maltasmvp      | 7248316 | 7247714 |    -602
           maltasmvp + r6 | 6955595 | 6950777 |   -4818
           pistachio      | 8650977 | 8363898 | -287079
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/16360/
      Cc: Joshua Kinard <kumba@gentoo.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      93e01942
    • Mathieu Malaterre's avatar
      MIPS: jz4780: DTS: Probe the spi-gpio driver from devicetree · c24f5762
      Mathieu Malaterre authored
      Make use of the spi-gpio driver to provide SPI support on the Ingenic
      JZ4780 SoC using the pins that can be used with the SSI0 device as
      GPIOs, until such time as we have support for the Ingenic SPI/SSI
      controller.
      
      [paul.burton@mips.com: Rewrite commit message.]
      Signed-off-by: default avatarMathieu Malaterre <malat@debian.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19489/
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: devicetree@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      c24f5762
    • Mathieu Malaterre's avatar
      MIPS: Ci20: Enable SPI/GPIO driver · 2e90396a
      Mathieu Malaterre authored
      Enable CONFIG_SPI_GPIO in ci20_defconfig, in order to make use of the
      spi-gpio driver in a further commit.
      
      [paul.burton@mips.com: Rewrite commit message.]
      Signed-off-by: default avatarMathieu Malaterre <malat@debian.org>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19488/
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: devicetree@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      2e90396a
    • Alexander Sverdlin's avatar
      MIPS: Octeon: Select HAS_RAPIDIO · 491ec155
      Alexander Sverdlin authored
      All Octeons starting with Octeon II have RAPIDIO controller which
      can function even with PCI disabled.
      Signed-off-by: default avatarAlexander Sverdlin <alexander.sverdlin@nokia.com>
      Acked-by: default avatarAlexandre Bounine <alex.bou9@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19988/
      Cc: linux-mips@linux-mips.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Matt Porter <mporter@kernel.crashing.org>
      491ec155
    • Alexander Sverdlin's avatar
      MIPS: Introduce HAS_RAPIDIO Kconfig option · fc5d9888
      Alexander Sverdlin authored
      Introduce the same option as PPC and ARM already have because
      RAPIDIO can function in the absence of PCI.
      Signed-off-by: default avatarAlexander Sverdlin <alexander.sverdlin@nokia.com>
      Acked-by: default avatarAlexandre Bounine <alex.bou9@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19987/
      Cc: linux-mips@linux-mips.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Matt Porter <mporter@kernel.crashing.org>
      fc5d9888
    • Thomas Petazzoni's avatar
      mips: use asm-generic version of msi.h · 34a4399f
      Thomas Petazzoni authored
      This is necessary to be able to include <linux/msi.h> when
      CONFIG_GENERIC_MSI_IRQ_DOMAIN is enabled. Without this, a build with
      CONFIG_GENERIC_MSI_IRQ_DOMAIN fails with:
      
         In file included from include/linux/kvm_host.h:20:0,
                          from arch/mips/kernel/asm-offsets.c:24:
      >> include/linux/msi.h:197:10: fatal error: asm/msi.h: No such file or directory
          #include <asm/msi.h>
                   ^~~~~~~~~~~
         compilation terminated.
         make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1
         make[2]: Target '__build' not remade because of errors.
         make[1]: *** [prepare0] Error 2
         make[1]: Target 'prepare' not remade because of errors.
         make: *** [sub-make] Error 2
      Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@bootlin.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19986/
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Hanna Hawa <hannah@marvell.com>
      34a4399f
    • Huacai Chen's avatar
      MIPS: Loongson64: Define and use some CP0 registers · 97ab1bb4
      Huacai Chen authored
      Defines CP0_CONFIG3, CP0_CONFIG6, CP0_PAGEGRAIN and use them in
      kernel-entry-init.h for Loongson64.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19264/
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <james.hogan@mips.com>
      Cc: linux-mips@linux-mips.org
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhuacai@gmail.com>
      97ab1bb4
    • Huacai Chen's avatar
      MIPS: Loongson: Add Loongson-3A R3.1 basic support · 7cff3f16
      Huacai Chen authored
      Loongson-3A R3.1 is the bugfix revision of Loongson-3A R3.
      
      All Loongson-3 CPU family:
      
      Code-name         Brand-name       PRId
      Loongson-3A R1    Loongson-3A1000  0x6305
      Loongson-3A R2    Loongson-3A2000  0x6308
      Loongson-3A R3    Loongson-3A3000  0x6309
      Loongson-3A R3.1  Loongson-3A3000  0x630d
      Loongson-3B R1    Loongson-3B1000  0x6306
      Loongson-3B R2    Loongson-3B1500  0x6307
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19263/
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <james.hogan@mips.com>
      Cc: linux-mips@linux-mips.org
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhuacai@gmail.com>
      7cff3f16
    • Paul Cercueil's avatar
      MIPS: jz4740: Bump zload address · c6ea7e97
      Paul Cercueil authored
      Having the zload address at 0x8060.0000 means the size of the
      uncompressed kernel cannot be bigger than around 6 MiB, as it is
      deflated at address 0x8001.0000.
      
      This limit is too small; a kernel with some built-in drivers and things
      like debugfs enabled will already be over 6 MiB in size, and so will
      fail to extract properly.
      
      To fix this, we bump the zload address from 0x8060.0000 to 0x8100.0000.
      
      This is fine, as all the boards featuring Ingenic JZ SoCs have at least
      32 MiB of RAM, and use u-boot or compatible bootloaders which won't
      hardcode the load address but read it from the uImage's header.
      Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Patchwork: https://patchwork.linux-mips.org/patch/19787/
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      c6ea7e97