- 21 Jun, 2019 40 commits
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Harry Wentland authored
DCN2.0 (Display Core Next) is the display block in Navi10. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiaojie Yuan authored
since it's firmware. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
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Leo Li authored
DC needs to include the soc bounding box when initializing HW resources. Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is required to define amdgpu_device. The solution here is to split the bounding box structs into a different header, then include it in both amdgpu_ucode.h, and relevant DC HW resource files. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Harry Wentland authored
[WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by:
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hersen wu authored
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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hersen wu authored
when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by:
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Hawking Zhang authored
was missed before. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Marek Olšák authored
Proper size is 0. v2: squash in whitespace fixes (Ernst Sjöstrand) Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Kevin Wang authored
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10 Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Jack Xiao authored
It would hit SMU fw bug without BACO enablement when audio driver put audio device to D3 state. Before the bug in SMU fw get fixed, enable BACO feature as WAR. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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Kevin Wang authored
the uclk dpm feature is not work well on all navi10 asic, use pp feature mask module parameter to control it. Signed-off-by:
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tiancyin authored
Reviewed-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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tiancyin authored
Include the interface version as well. Signed-off-by:
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Alex Deucher authored
Fix UTCL1_CGTT_CLK_CTRL Signed-off-by: -
Alex Deucher authored
Use the SMU_* variant so we look up the correct index. Signed-off-by: -
Leo Liu authored
This is default mode for VCN2.x now Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
SRAM will be programmed by PSP Signed-off-by:
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Leo Liu authored
This will be used later for indirect SRAM mode Signed-off-by:
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Jack Xiao authored
SMU FW has bug that it would cause hung when both fw dstate and gfxoff are enabled at the same time. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jack Xiao authored
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.23 Signed-off-by:
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Jack Xiao authored
PSP leverages the existing fw loading function for vcn updating sram. Signed-off-by:
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Jack Xiao authored
Convert ucode id to the corresponding psp ucode id. Signed-off-by:
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Jack Xiao authored
Add VCN RAM ucode id in corresponding to psp ucode id. Signed-off-by:
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Jack Xiao authored
PSP supports to program vcn sram by ucode loading interface. Signed-off-by:
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Leo Liu authored
It will be the default for VCN2.x family Signed-off-by:
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Leo Liu authored
Pause the DPG when not doing decode Signed-off-by:
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Leo Liu authored
This is for using SRAM directly v2: rebase (Alex) Signed-off-by:
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Leo Liu authored
This will be the basic and used for DPG mode Signed-off-by:
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Leo Liu authored
Just for cleanup Signed-off-by:
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Kevin Wang authored
the od_settings is asic related data, so move it to asic file. Signed-off-by:
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Kevin Wang authored
the set default od_setting is asic related function, so move thic code to vega20_ppt file. Signed-off-by:
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Kevin Wang authored
these callback functions is only used for vega20 asic, to be compatible other asics,need to move this code to vega20_ppt file Signed-off-by:
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Kevin Wang authored
use sw-smu clk type name to replace legacy clk type name Signed-off-by:
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Kevin Wang authored
the smu->mutex is internal lock resource in sw-smu, some functions will use it at the same time, so it maybe will cause deadlock issue. this patch fix this issue in smu_force_performance_level function. Signed-off-by:
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Jack Xiao authored
The dummy page for returning from PRT resides inside system memory, need set system flag bit in VM_L2_CNTL. Signed-off-by:
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tiancyin authored
add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL, update registers: mmDB_DEBUG4, mmUTCL1_CTRL Reviewed-by:
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Alex Deucher authored
Signed-off-by: -
hersen wu authored
dc needs get uclk dpm table for bandwidth calculation Signed-off-by:
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hersen wu authored
this is hw workaround to wake up azalia from d3. display asic and azalia are two different pci devices. while display asic wake from d3, current hw does not send signal to azalia. workaround: display driver ask smu send message to azalia device to let azalia wake up. Defintion of SMU message, like PPSMC_MSG_BacroAudioD3PME, is per asic. It is shared by different OS. Signed-off-by:
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hersen wu authored
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by:
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