- 03 Nov, 2021 24 commits
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Jake Wang authored
[Why & How] The MPC memory clocks should be powered down when not in use. Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jake Wang authored
[Why] HPO is only used for DP2.0. HPO HW control should be disable when not being used to save power. [How] Shutdown HPO HW control during init hw. Shutdown HPO HW control during stream disable. Enable HPO HW control during stream enable if DP2.0. Acked-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Tested-by:
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Wenjing Liu authored
[why&how] write LINK_SQUARE_PATTERN_num + 1 for square pulse pattern. Specs requirement to write this register prior to write LINK_QUAL_LANEX_SET. Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] State can be cleared without removing individual streams (by calling dc_remove_stream_from_ctx()). This can leave the encoder assignment module in an incoherent state and cause future assignments to be incorrect. [How] Clear encoder assignments when committing 0 streams or re-initializing hardware. Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Tested-by:
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Roman Li authored
[Why] In scenario when 1 display connected with pipe split (2 pipes in use) and 3 new displays simultaneously hotplugged via MST hub (4 pipes in use), mpcc may get reprogram to other vtg, remaining busy. In this case waiting for mpcc idle timeouts with error like this: [drm] REG_WAIT timeout 1us * 100000 tries - mpc2_assert_idle_mpcc RIP: 0010:mpc2_assert_mpcc_idle_before_connect Call Trace: dcn20_update_mpcc dcn20_program_front_end_for_ctx dc_commit_state amdgpu_dm_atomic_commit_tail ... [How] Add pipe split change condition to disable dangling plane. Acked-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Bing Guo authored
[Why] 1. YCbCr 4:2:2 8bpc/10bpc modes are blocked for HDMI by policy 2. A YCbCr 4:2:0 calculation error blocked some 4:2:0 timing modes [How] YCbCr 4:2:2 8bpc/10bpc modes are allowed for HDMI Fix YCbCr 4:2:0 calculation error Acked-by:
Bing Guo <Bing.Guo@amd.com> Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
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Yu-ting Shen authored
[Why] MST monitor sends link loss short pulse continuous but sink is occupy by HDMI input to lead link training fail. [How] disable link once retraining fail. Acked-by:
Yu-ting Shen <yu-tshen@amd.com> Reviewed-by:
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Felipe Clark authored
[WHY] It was found that the system would hang on a dummy pstate when playing 4k60 videos on a 1080p 390Hz monitor. [HOW] Properly select the dummy_pstate_latency_ms when firmware assisted memory clock switching is enabled instead of assuming that the highest latency would work for every monitor timing. Acked-by:
Felipe Clark <felclark@amd.com> Reviewed-by:
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Anson Jacob authored
Fix spacing issue for the format string. Addresses-Coverity-ID: 1446765: ("Invalid printf format string") Acked-by:Anson Jacob <Anson.Jacob@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Hersen Wu authored
[WHY] If timing and bpp of displays on mst hub are not changed, pbn, slot_num for displays should not be changed. Linux user mode may initiate atomic_check with different display configuration after set mode finished. This will call to amdgpu_dm to re-compute payload, slot_num of displays and saved to dm_connect_state. stream->timing.flags.dsc, pbn, slot_num are updated to values which may be different from that were used for set mode. when dsc hub with 3 4k@60hz dp connected, 3 dsc engines are enabled. timing.flags.dsc = 1. timing.flags.dsc are changed to 0 due to atomic check. when dsc hub is unplugged, amdgpu driver check timing.flags.dsc for last mode set and find out flags.dsc = 0, then does not disable dsc. [HOW] check status of displays on dsc mst hubs. re-compute pbn, slot_num, timing.flags.dsc only if there is mode, connect or enable/disable change. Acked-by:
Hersen Wu <hersenwu@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Tested-by:
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James Zhu authored
Remove duplicated kfd_resume_iommu which already runs in mdgpu_amdkfd_device_init. Tested-By:
Ken Moffat <zarniwhoop@ntlworld.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Aaron Liu authored
For yellow carp, the desired CGPG hysteresis value is 0x4E20. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Mario Limonciello authored
commit 652de07a ("drm/amd/display: Fully switch to dmub for all dcn21 asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this implied a new dependency on newer firmware which might not be met on older kernel versions. Since sw_init runs before hw_init, there is an opportunity to determine whether or not the firmware version is new to adjust the behavior. Cc: Roman.Li@amd.com BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1772 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1735 Fixes: 652de07a ("drm/amd/display: Fully switch to dmub for all dcn21 asics") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Mario Limonciello authored
For ASICs not supporting power profile mode, don't show the attribute. Verify that the function has been implemented by the subsystem. Suggested-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Mario Limonciello authored
This better aligns that the caller can make a mistake with the buffer and -EINVAL should be returned, but if the hardware doesn't support the feature it should be -EOPNOTSUPP. Signed-off-by:
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Mario Limonciello authored
Prevent possible issues from set and get being called simultaneously. Signed-off-by:
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Mario Limonciello authored
This was added by commit bd8dcea9 ("drm/amd/pm: add callbacks to read/write sysfs file pp_power_profile_mode") but the feature was deprecated from PMFW. Remove it from the driver. Signed-off-by:
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Graham Sider authored
Previously Renoir compiler gfx target version was forced to Raven. Update driver side for completeness. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
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Mario Limonciello authored
This is more useful when talking to the SMU team to have the information in this format, save one less step to manually do it. Reviewed-by:
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Felix Kuehling authored
If some pages fail to migrate to system memory, don't update prange->actual_loc = 0. This prevents endless CPU page faults after partial migration failures due to contested page locks. Migration to RAM must be complete during migrations from VRAM to VRAM and during evictions. Implement retry and fail if the migration to RAM fails. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Felix Kuehling authored
Stack and heap pages tend to be shared by many small allocations. Concurrent access by CPU and GPU is therefore likely, which can lead to thrashing. Avoid this by setting the preferred location to system memory. Signed-off-by:
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Felix Kuehling authored
The preferred location should be used as the migration destination whenever it is accessible by the faulting GPU. System memory is always accessible. Peer memory is accessible if it's in the same XGMI hive. Signed-off-by:
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Oak Zeng authored
Aldebaran has different register mask definitions for regiter MC_VM_XGMI_LFB_CNTL. Use the correct masks to interpret fields of this register. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jingwen Chen authored
[Why] In advance tdr mode, the real bad job will be resubmitted twice, while in drm_sched_resubmit_jobs_ext, there's a dma_fence_put, so the bad job is put one more time than other jobs. [How] Adding dma_fence_get before resbumit job in amdgpu_device_recheck_guilty_jobs and put the fence for normal jobs Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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- 02 Nov, 2021 1 commit
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Dave Airlie authored
Merge tag 'amd-drm-next-5.16-2021-10-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.16-2021-10-29: amdgpu: - RAS fixes - Fix a potential memory leak in device tear down - Add a stutter mode quirk - Misc display fixes - Further display FP refactoring - Display USB4 fixes - Display DP2.0 fixes - DCN 3.1 fixes - Display 8 ch audio fix - Fix DMA mask regression for SI parts - Aldebaran fixes amdkfd: - userptr fix - BO lifetime fix - Misc code cleanup UAPI: - Minor header cleanup (no functional change) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211029184338.4863-1-alexander.deucher@amd.com
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- 28 Oct, 2021 15 commits
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Alex Deucher authored
The DMA mask on SI parts is 40 bits not 44. Copy paste typo. Fixes: 244511f3 ("drm/amdgpu: simplify and cleanup setting the dma mask") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1762Acked-by:
Christian König <christian.koenig@amd.com> Tested-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] - DPIA MST slot registers are not programmed during payload allocation and hence MST does not work with DPIA. - HPD RX interrupts are not handled for DPIA. [How] - Added inbox command to program the MST slots whenever payload allocation happens for DPIA links. - Added support for handling HPD RX interrupts Signed-off-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
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Patrik Jakobsson authored
CVE-2021-42327 was fixed by: commit f23750b5 Author: Thelford Williams <tdwilliamsiv@gmail.com> Date: Wed Oct 13 16:04:13 2021 -0400 drm/amdgpu: fix out of bounds write but amdgpu_dm_debugfs.c contains more of the same issue so fix the remaining ones. v2: * Add missing fix in dp_max_bpc_write (Harry Wentland) Fixes: 918698d5 ("drm/amd/display: Return the number of bytes parsed than allocated") Signed-off-by:
Patrik Jakobsson <pjakobsson@suse.de> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Add secondary instance version info for soc15 parts. Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Alex Deucher authored
Add secondary instance version info for vega20, arcturure, and aldebaran. Acked-by:
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Alex Deucher authored
Move the RAS query parameters to align with the INFO query where they are used. No functional change. Reviewed-by:
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Jude Shih authored
[Why] DMUB binary is common for both A0 and B0. Hence, driver should notify FW about the support for DPIA in B0. [How] Added dpia_supported bit in dmub_fw_boot_options and will be set only for B0. Assign dpia_supported to true before dm_dmub_hw_init in B0 case. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Signed-off-by:
Jude Shih <shenshih@amd.com> Reviewed-by:
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Jude Shih authored
[Why] Notify data from outbox corrupt, the notify type should be 2 (HPD) instead of 0 (No data). We copied the address instead of the value. The memory might be freed in the end of outbox IRQ [How] We should allocate the memory of notify and copy the whole content from outbox to hpd handle function Fixes: 88f52b1f ("drm/amd/display: Support for SET_CONFIG processing with DMUB") Signed-off-by:
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Nicholas Kazlauskas authored
[Why] A deadlock in the kernel occurs when we fallback from the V3 to V2 add_topology_to_display or remove_topology_to_display because they both try to acquire the dtm_mutex but recursive locking isn't supported on mutex_lock(). [How] Make the mutex_lock/unlock more fine grained and move them up such that they're only required for the psp invocation itself. Fixes: bf62221e ("drm/amd/display: Add DCN3.1 HDCP support") Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] On certain configs, SMU clock table voltages don't match which cause parser to behave incorrectly by leaving dcfclk and socclk table entries unpopulated. [HOW] Currently the function that finds the corresponding clock for a given voltage only checks for exact voltage level matches. In the case that no match gets found, parser now falls back to searching for the max clock which meets the requested voltage (i.e. its corresponding voltage is below requested). Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Qingqing Zhuo authored
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN301 to DML, where all FPU code should locate. Cc: Christian König <christian.koenig@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
Zhan Liu <Zhan.Liu@amd.com> Tested-by:
Qingqing Zhuo <Qingqing.Zhuo@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] We have a regression that cause maximize lane settings to use uninitialized data from unused lanes. This will cause link training to fail for 1 or 2 lanes because the lane adjust is populated incorrectly sometimes. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Reviewed-by:
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Wenjing Liu authored
[why] option 1: disallow different lanes to have different lane settings option 2: dpcd lane settings will always use the same hw lane settings even if it doesn't match requested lane adjust Reviewed-by:
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Wenjing Liu authored
[why] As DP features expands, we have encountered many situations where we must configure a different DPCD lane setting from hw lane settings we output. The change is to decouple hw lane settings from dpcd lane settings to provide flexibility to configure dpcd and hw individually. Reviewed-by:
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Wenjing Liu authored
[why] Decouple lane settings decision logic all to its own function. The function takes in lane adjust array and link training settings and decide what hw lane setting and dpcd lane setting should be used. Reviewed-by:
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