- 12 Jun, 2019 17 commits
-
-
Russell King authored
When a GPIO block has the set/clear dataout registers implemented, it also has the normal dataout register implemented. Reading this register reads the current GPIO output state, and writing it sets the GPIOs to the explicit state. This is the behaviour that we want when saving and restoring the context, so use the dataout register exclusively. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Tested-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Russell King authored
omap_set_gpio_irqenable() calls two helpers that are almost the same apart from whether they set or clear bits. We can consolidate these: - in the set/clear bit register case, we can perform the operation on our saved context copy and write the appropriate set/clear register. - otherwise, we can use our read-modify-write helper and invert enable if irqenable_inv is set. Signed-off-by:
-
Russell King authored
This function open-codes an exclusive-or bitwise operation using an if() statement and explicitly setting or clearing the bit. Instead, use an exclusive-or operation instead, and simplify the function. We can combine the preprocessor conditional using IS_ENABLED() and gain some additional compilation coverage. Signed-off-by:
-
Russell King authored
We already have a read-modify-write helper, but there's more that can be done with a read-modify-write helper if it returned the new value. Modify the existing helper to return the new value, and arrange for it to take one less argument by having the caller compute the register address. Signed-off-by:
-
Russell King authored
bank->level_mask is merely the bitwise or of the level detection context which we have already read in this function. Rather than repeating additional reads, compute it from the values already read. Signed-off-by:
-
Russell King authored
One of the reasons for set_multiple() to exist is to allow multiple GPIOs on the same chip to be changed simultaneously - see commit 5f424243 ("gpiolib: allow simultaneous setting of multiple GPIO outputs"): - Simultaneous glitch-free setting of multiple pins on any kind of parallel bus attached to GPIOs provided they all reside on the same chip and bank. In order for this to work, we should not use the atomic set/clear registers, but instead read-modify-write the dataout register. We already take the spinlock to ensure that happens atomically, so move the code into the set_multiple() function and kill the two helper functions. Signed-off-by:
-
Russell King authored
There is no reason to have helper functions to read the datain and dataout registers when they are only used in one location. Simplify this code to make it more readable. Signed-off-by:
-
Russell King authored
omap_gpio_get() calls omap_get_gpio_datain() or omap_get_gpio_dataout() to read the GPIO state. These two functions are only called from this method, so they don't add much value. Move their contents into omap_gpio_get() method and simplify. Signed-off-by:
-
Russell King authored
Architectures are single-copy atomic, which means that simply reading a register is an inherently atomic operation. There is no need to take a spinlock here. Signed-off-by:
-
Russell King authored
Move these two functions to live beside the rest of the gpio chip implementation, rather than in the middle of the irq chip implementation. Signed-off-by:
-
Russell King authored
The irq_ack method does not fit our hardware requirements. Edge interrupts must be cleared before we handle them, and level interrupts must be cleared after handling them. We handle the interrupt clearance in our interrupt handler for edge IRQs and in the unmask method for level IRQs. Replace the irq_ack method with the no-op method from the dummy irq chip. Signed-off-by:
-
Russell King authored
The edge interrupt handling was effectively: isr = ISR_reg & enabled; if (bank->level_mask) level_mask = bank->level_mask & enabled; else level_mask = 0; edge = isr & ~level_mask; When bank->level_mask is zero, level_mask will be computed as zero anyway, so the if() statement is redundant. We are then left with: isr = ISR_reg & enabled; level_mask = bank->level_mask & enabled; edge = isr & ~level_mask; This can be simplified further to: isr = ISR_reg & enabled; edge = isr & ~bank->level_mask; since the second mask with 'enabled' is redundant. Improve the associated comment as well. Signed-off-by:
-
Russell King authored
Commit c4791bc6 ("gpio: omap: drop omap_gpio_list") removed the list head and addition to the list head of each gpio bank, but failed to remove the list_del() call and the node inside struct gpio_bank. Remove these too. Fixes: c4791bc6 ("gpio: omap: drop omap_gpio_list") Signed-off-by:
-
Russell King authored
Commit 384ebe1c ("gpio/omap: Add DT support to GPIO driver") added the register definition tables to the gpio-omap driver. Subsequently to that commit, commit 4e962e89 ("gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume()") added definitions for irqstatus_raw* registers to the legacy OMAP4 definitions, but missed the DT definitions. This causes an unintentional change of behaviour for the 1.101 errata workaround on OMAP4 platforms. Fix this oversight. Fixes: 4e962e89 ("gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume()") Signed-off-by:
-
Russell King authored
Documentation states: NOTE: There must be a correlation between the wake-up enable and interrupt-enable registers. If a GPIO pin has a wake-up configured on it, it must also have the corresponding interrupt enabled (on one of the two interrupt lines). Ensure that this condition is always satisfied by enabling the detection events after enabling the interrupt, and disabling the detection before disabling the interrupt. This ensures interrupt/wakeup events can not happen until both the wakeup and interrupt enables correlate. If we do any clearing, clear between the interrupt enable/disable and trigger setting. Signed-off-by:
-
Linus Walleij authored
-
Martin Blumenstingl authored
The stmmac driver currently ignores the GPIO flags which are passed via devicetree because it operates with legacy GPIO numbers instead of GPIO descriptors. stmmac assumes that the GPIO is "active HIGH" by default. This can be overwritten by setting "snps,reset-active-low" to make the reset line "active LOW". Recent Amlogic SoCs (G12A which includes S905X2 and S905D2 as well as G12B which includes S922X) use GPIOZ_14 or GPIOZ_15 for the PHY reset line. These GPIOs are special because they are marked as "3.3V input tolerant open drain" pins which means they can only drive the pin output LOW (to reset the PHY) or to switch to input mode (to take the PHY out of reset). The GPIO subsystem already supports this with the GPIO_OPEN_DRAIN and GPIO_OPEN_SOURCE flags in the devicetree bindings. Add the stmmac PHY reset line specific active low parsing to gpiolib-of so stmmac can be ported to GPIO descriptors while being backwards compatible with device trees which use the "old" way of specifying the polarity. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
-
- 10 Jun, 2019 3 commits
-
-
Phil Reid authored
Keeping the irq_chip definition static shares it with multiple instances of the altera gpiochip in the system. This is bad and now we get this warning from gpiolib core: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the irq_chip definition from being driver static into the struct altera_gpio_chips. So a unique irq_chip is used for each gpiochip instance. Signed-off-by:
Phil Reid <preid@electromag.com.au> Signed-off-by:
-
Robert Hancock authored
This driver was using the OF GPIO helper API, but barely used any of its features and it cost more code than it saved. Also, the OF GPIO code is now deprecated. Convert it to use a more standard setup and use devm APIs for initialization to avoid the need for a remove function. Our rationale for this change is that we are using the Xilinx GPIO with resources injected using the MFD core rather than on the device tree itself. Using platform rather than OF-specific resources allows this to work for free. Signed-off-by:
Robert Hancock <hancock@sedsystems.ca> Acked-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
-
Linus Walleij authored
FMC has its own GPIO handling, the inclusion of <linux/gpio.h> is only to reuse some flags that we can just as well provide using local defines. Cc: Federico Vaga <federico.vaga@cern.ch> Cc: Pat Riehecky <riehecky@fnal.gov> Acked-by:
Alessandro Rubini <rubini@gnudd.com> Signed-off-by:
-
- 07 Jun, 2019 6 commits
-
-
Keerthy authored
The patch adds k3 am654 compatible, specific properties and an example. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
-
Keerthy authored
Add new compatible for K3 AM654 SoCs. Signed-off-by:
-
Keerthy authored
Add K3 dependencies to enable the driver on K3 platforms. Signed-off-by:
-
Keerthy authored
Fix the compiler warning with ARM64 config enabled as the current mask assumes 32 bit by default. Signed-off-by:
-
Linus Walleij authored
When a gpio_chip wants to request a descriptor from itself using gpiochip_request_own_desc() it needs to be able to specify fully how to use the descriptor, notably line inversion semantics. The workaround in the gpiolib.c can be removed and cases (such as SPI CS) where we need at times to request a GPIO with line inversion semantics directly on a chip for workarounds, can be fully supported with this call. Fix up some users of the API that weren't really using the last flag to set up the line as input or output properly but instead just calling direction setting explicitly after requesting the line. Cc: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: -
Mauro Carvalho Chehab authored
With ReST, [foo]_ means a reference to foo, causing this warning: Documentation/driver-api/gpio/driver.rst:419: WARNING: Unknown target name: "devm". Fix it by using a literal for the name. Signed-off-by:Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Signed-off-by:
-
- 02 Jun, 2019 1 commit
-
-
Peter Robinson authored
The TI TCA9539 is a variant of the PCA953x GPIO expander, with 16 GPIOs and interrupt functionality. Signed-off-by:
Peter Robinson <pbrobinson@gmail.com> Signed-off-by:
-
- 31 May, 2019 1 commit
-
-
Linus Walleij authored
The Freescale SPI chipselects are special: while everyone else is using "cs-gpios" the Freescale platforms just use "gpios". Fix this by responding with "gpios" when asking for "cs-gpios" in a freescale device node, so we hide this pecularity from the SPI core. Signed-off-by:
-
- 28 May, 2019 6 commits
-
-
Rob Herring authored
Convert the Arm PL061 GPIO controller binding to json-schema format. As I'm the author for all but the gpio-ranges line, make the schema dual GPL/BSD license. Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: linux-gpio@vger.kernel.org Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Luca Ceresoli authored
The 'default (active high)' lines are repeated twice. Avoid people stare at their screens looking for differences. Signed-off-by:
Luca Ceresoli <luca@lucaceresoli.net> Reviewed-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by:
-
Linus Walleij authored
Use standard functions. Eventually we will be able to drop all checks and just assign irq_domain_translate_twocell() to this callback. Cc: Brian Masney <masneyb@onstation.org> Signed-off-by: -
Linus Walleij authored
This fixes up some of my own mistakes when I stressed to refresh the documentation. Signed-off-by: -
Linus Walleij authored
This feature is deprecated, it is helpful to inform users about this. I'm resisting the temptation to add "depends on BROKEN" to this, but saving that for later. Reviewed-by:
-
Andrey Smirnov authored
Simplify error checking code by replacing multiple ERR macros with a call to PTR_ERR_OR_ZERO. No functional change intended. Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by:
-
- 26 May, 2019 6 commits
-
-
Linus Torvalds authored
-
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-traceLinus Torvalds authored
Pull tracing warning fix from Steven Rostedt: "Make the GCC 9 warning for sub struct memset go away. GCC 9 now warns about calling memset() on partial structures when it goes across multiple fields. This adds a helper for the place in tracing that does this type of clearing of a structure" * tag 'trace-v5.2-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace: tracing: Silence GCC 9 array bounds warning
-
git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull KVM fixes from Paolo Bonzini: "The usual smattering of fixes and tunings that came in too late for the merge window, but should not wait four months before they appear in a release. I also travelled a bit more than usual in the first part of May, which didn't help with picking up patches and reports promptly" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (33 commits) KVM: x86: fix return value for reserved EFER tools/kvm_stat: fix fields filter for child events KVM: selftests: Wrap vcpu_nested_state_get/set functions with x86 guard kvm: selftests: aarch64: compile with warnings on kvm: selftests: aarch64: fix default vm mode kvm: selftests: aarch64: dirty_log_test: fix unaligned memslot size KVM: s390: fix memory slot handling for KVM_SET_USER_MEMORY_REGION KVM: x86/pmu: do not mask the value that is written to fixed PMUs KVM: x86/pmu: mask the result of rdpmc according to the width of the counters x86/kvm/pmu: Set AMD's virt PMU version to 1 KVM: x86: do not spam dmesg with VMCS/VMCB dumps kvm: Check irqchip mode before assign irqfd kvm: svm/avic: fix off-by-one in checking host APIC ID KVM: selftests: do not blindly clobber registers in guest asm KVM: selftests: Remove duplicated TEST_ASSERT in hyperv_cpuid.c KVM: LAPIC: Expose per-vCPU timer_advance_ns to userspace KVM: LAPIC: Fix lapic_timer_advance_ns parameter overflow kvm: vmx: Fix -Wmissing-prototypes warnings KVM: nVMX: Fix using __this_cpu_read() in preemptible context kvm: fix compilation on s390 ...
-
git://git.kernel.org/pub/scm/linux/kernel/git/tytso/randomLinus Torvalds authored
Pull /dev/random fix from Ted Ts'o: "Fix a soft lockup regression when reading from /dev/random in early boot" * tag 'random_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/random: random: fix soft lockup when trying to read from an uninitialized blocking pool
-
Theodore Ts'o authored
Fixes: eb9d1bf0: "random: only read from /dev/random after its pool has received 128 bits" Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Theodore Ts'o <tytso@mit.edu>
-
Miguel Ojeda authored
Starting with GCC 9, -Warray-bounds detects cases when memset is called starting on a member of a struct but the size to be cleared ends up writing over further members. Such a call happens in the trace code to clear, at once, all members after and including `seq` on struct trace_iterator: In function 'memset', inlined from 'ftrace_dump' at kernel/trace/trace.c:8914:3: ./include/linux/string.h:344:9: warning: '__builtin_memset' offset [8505, 8560] from the object at 'iter' is out of the bounds of referenced subobject 'seq' with type 'struct trace_seq' at offset 4368 [-Warray-bounds] 344 | return __builtin_memset(p, c, size); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ In order to avoid GCC complaining about it, we compute the address ourselves by adding the offsetof distance instead of referring directly to the member. Since there are two places doing this clear (trace.c and trace_kdb.c), take the chance to move the workaround into a single place in the internal header. Link: http://lkml.kernel.org/r/20190523124535.GA12931@gmail.comSigned-off-by:Miguel Ojeda <miguel.ojeda.sandonis@gmail.com> [ Removed unnecessary parenthesis around "iter" ] Signed-off-by:
Steven Rostedt (VMware) <rostedt@goodmis.org>
-
