- 16 Jan, 2014 2 commits
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Sherman Yin authored
Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. v4: Changed valid values for "bias-pull-up" property for I2C pins. Expanded pin configuration node example. v3: Use generic pin config properties instead of brcm-specific ones. Clarified pin types (standard, i2c, hdmi). v2: Use hyphens instead of underscore in DT property names. Device tree bindings maintainers ECG: _ _ _ _ _ __________/ \ ________/ \ _____/ \ ___/ \ ___/ \ __ \_/ \_/ \_/ \_/ \_/ Signed-off-by:Sherman Yin <syin@broadcom.com> Reviewed-by:
Christian Daudt <bcm@fixthebug.org> Reviewed-by:
Matt Porter <matt.porter@linaro.org> Acked-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Sherman Yin authored
drv_data is added to the pinctrl_pin_desc for drivers to define additional driver-specific per-pin data. Signed-off-by:
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- 15 Jan, 2014 8 commits
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Srinivas Kandagatla authored
Probe function had commas instead of semi-colons on some of the lines. This patch just fixes those lines. No functional chagnes done in this patch. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by:
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Laszlo Papp authored
I had been trying to learn a bit more about the pinctrl subsystem, and I realized several typos and grammar issues while going through the documentation. I have probably not caught all the possible issues, but this change is addressing several places for improvement. Signed-off-by:
Laszlo Papp <lpapp@kde.org> Signed-off-by:
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Linus Walleij authored
This uses the new API for tagging GPIO lines as in use by IRQs. This enforces a few semantic checks on how the underlying GPIO line is used. Also assign the gpio_chip.dev pointer to be used for error messages. Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: -
Barry Song authored
busses like i2c, spi and so on can parse the virq of their subnode automatically by irq_of_parse_and_map(). for example, i2c will do that in of_i2c_register_devices(). people can put hwirq number attached to a gpio controller in dts, and drivers can directly request the parsed virq. for example, for an i2c client as below, tangoc-ts@5c{ compatible = "pixcir,tangoc-ts"; interrupt-parent = <&gpio>; interrupts = <3 0>; reg = <0x5c>; }; in i2c client probe(), it will request_irq(client->irq, ...) without calling gpio_direction_input(). so here when we set irq type, we also put the pin to input direction. Signed-off-by:Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Barry Song authored
in sirfsoc gpio probe(), we create 5 irq_domains for 5 gpio banks. but in irq_create_of_mapping() of irqchip core level, irq_find_host() can only return the 1st irq_domain attached the pinctrl dt device node as we can see from the codes: unsigned int irq_create_of_mapping(struct device_node *controller, const u32 *intspec, unsigned int intsize) { struct irq_domain *domain; ... domain = controller ? irq_find_host(controller) : irq_default_domain; } struct irq_domain *irq_find_host(struct device_node *node) { struct irq_domain *h, *found = NULL; int rc; /* We might want to match the legacy controller last since * it might potentially be set to match all interrupts in * the absence of a device node. This isn't a problem so far * yet though... */ mutex_lock(&irq_domain_mutex); list_for_each_entry(h, &irq_domain_list, link) { if (h->ops->match) rc = h->ops->match(h, node); else rc = (h->of_node != NULL) && (h->of_node == node); if (rc) { found = h; break; } } mutex_unlock(&irq_domain_mutex); return found; } for sirfsoc, the 1st irq_domain attached to the device_node(controller) only can do linear for the 1st 32 gpios. so for devices who use gpio hwirq above 32 and put the information in dt like: tangoc-ts@5c{ compatible = "pixcir,tangoc-ts"; + interrupt-parent = <&gpio>; + interrupts = <34 0>; }; we will fail to get the virq for these devices as hwirq will be bigger than domain->revmap_data.linear.size in: unsigned int irq_linear_revmap(struct irq_domain *domain, irq_hw_number_t hwirq) { /* Check revmap bounds; complain if exceeded */ if (WARN_ON(hwirq >= domain->revmap_data.linear.size)) return 0; return domain->revmap_data.linear.revmap[hwirq]; } this patch drops redundant irq_domain and keep only one to fix the problem. Signed-off-by: -
Tomi Valkeinen authored
commit 4e7e8017 (pinctrl: pinctrl-single: enhance to configure multiple pins of different modules) improved support for pinctrl-single,bits option, but also caused a regression in parsing badly configured mask data. If the masks in DT data are not quite right, pcs_parse_bits_in_pinctrl_entry() can end up in an infinite loop, trashing memory at the same time. Add a check to verify that each loop actually removes bits from the 'mask', so that the loop can eventually end. Signed-off-by:
Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Tomi Valkeinen authored
pcs_enable() uses vals->mask instead of pcs->fmask when bits_per_mux is enabled. However, pcs_disable() always uses pcs->fmask. Fix pcs_disable() to use vals->mask with bits_per_mux. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by:
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Tomi Valkeinen authored
Remove extra comma in pinctrl-single documentation. Signed-off-by:
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- 14 Jan, 2014 1 commit
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Mallikarjun Kasoju authored
If pins are used for function output like pwm, clk32k, power good etc then set it as output mode default. Signed-off-by:
Mallikarjun Kasoju <mkasoju@nvidia.com> Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Acked-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
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- 08 Jan, 2014 5 commits
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Rongjun Ying authored
USP0 has multiple functions, and has RX and TX frame sync signals, for some scenarios like audio PCM, we don't need both of them. so here we add two possibilities for USP0 only holding one of TX and RX frame sync. Signed-off-by:
Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by:
Barry Song <Barry.Song@csr.com> Signed-off-by:
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Bin Shi authored
sdmmc5 has only 3 pins CMD, CLK, DATA which are connected with CSR TriG RF multi-GNSS. The hardware connection is like: DATA -- GPS_SGN CLK -- GPS_RF_CLK CMD -- GPS_MAG here we drop redundant pins in sdmmc5 group. Signed-off-by:
Bin Shi <Bin.Shi@csr.com> Signed-off-by:
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Qipan Li authored
commit af614b23 adds lost USP-based UART pin groups for prima2, but missed usp1_uart_nostreamctrl group for atlas6, this patch fixes it. this makes USP(Universal Serial Ports) port1 can work as uart without stream ctrl. Signed-off-by:
Qipan Li <Qipan.Li@csr.com> Signed-off-by:
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Chen-Yu Tsai authored
This patch adds the clock output pin functions on the A20. The 2 pins can output a configurable clock to be used by external modules. This is used on the CubieTruck, to supply a 32768 Hz low power clock to the onboard Wifi+BT module. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Antonios Vamporakis authored
Signed-off-by:
Antonios Vamporakis <ant@area128.com> CC: John Crispin <blogic@openwrt.org> Signed-off-by:
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- 07 Jan, 2014 4 commits
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Valentine Barshak authored
This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by:
Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Valentine Barshak authored
This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by:
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Valentine Barshak authored
This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by:
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Valentine Barshak authored
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by:
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- 20 Dec, 2013 5 commits
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Laurent Pinchart authored
The arrays are never modified, declare them as const. Signed-off-by:
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Laurent Pinchart authored
The arrays are never modified, declare them as const. Signed-off-by:
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Laurent Pinchart authored
The arrays are never modified, make them const. Signed-off-by:
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Laurent Pinchart authored
The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by:
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Axel Lin authored
Set g->out_bit bit for gpio output high, clear g->out_bit bit for gpio output low. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
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- 16 Dec, 2013 8 commits
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Boris BREZILLON authored
Replace the clk_prepare and clk_enable calls by a single clk_prepare_enable call. Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Boris BREZILLON authored
clk_unprepare shall be called before clk_disable. Fix the issue by replacing the clk_unprepare and clk_disable calls by a single clk_disable_unprepare call. Signed-off-by:
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Sherman Yin authored
This commit adds slew-rate and input-enable/disable support for pinconf -generic. Signed-off-by:
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Bjorn Andersson authored
Use the more specific form 8974 for the compatible to reduce the risk of future mishaps. Signed-off-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Bjorn Andersson authored
Make the bitmaps part of the msm_pinctrl allocation instead of separately allocating them. Signed-off-by:
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Bjorn Andersson authored
Signed-off-by:
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Bjorn Andersson authored
Signed-off-by:
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Bjorn Andersson authored
Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix build errors from i386-randconfig. Also add help text and make the entries tristate, while touching these entries. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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- 13 Dec, 2013 2 commits
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Alexandre Belloni authored
Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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Alexandre Belloni authored
This allows to get the pin configuration by using debugfs. On my system: # cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pins Signed-off-by:
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- 12 Dec, 2013 5 commits
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Ashwini Ghuge authored
This adds a driver for the Tegra124 pinmux, and required parameterization data for Tegra124. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra124-pinmux". Originally written by Ashwini Gguhe. Thierry: - Cleanups in patches. ldewangan: - Fix some entries for groups. - Fix MUX enums and group sequence. Signed-off-by:
Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com> Tested-by:
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Laxman Dewangan authored
This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Changes from V1: - Referred the dt-binding header file on describing the nodes. Changes from V2: - Rewording reg properties. - drop drv_type as it is not applicable. Signed-off-by:
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Laurent Pinchart authored
On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Laurent Pinchart authored
There's more than one window, name the field windows. Signed-off-by:
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Laurent Pinchart authored
This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by:
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