- 01 Jun, 2010 1 commit
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Adam Jackson authored
I'm actually kind of shocked that it works at all otherwise. Signed-off-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
Eric Anholt <eric@anholt.net>
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- 28 May, 2010 16 commits
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Zhenyu Wang authored
With splitted engines on Sandybridge, each engine has its own interrupt control as well. This unmasks the interrupt to properly enable pipe control notify event for render engine. Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
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Zhenyu Wang authored
Sandybridge(Gen6) has new format for PIPE_CONTROL command, the flush and post-op control are in dword 1 now. This changes command length field for difference between Ironlake and Sandybridge. I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify interrupts, which seems work fine. Hopefully we don't need workaround like on Ironlake for Sandybridge. Signed-off-by:
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Chris Wilson authored
Since we now get_user_pages() outside of the mutex prior to performing the copy, we kmap() the page inside the copy routine and so need to perform an ordinary memcpy() and not copy_from_user(). Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
As we do not have a requirement to be atomic and avoid sleeping whilst performing the slow copy for shmem based pread and pwrite, we can use kmap instead, thus simplifying the code. Signed-off-by:
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Chris Wilson authored
We can avoid an early clflush when pwriting if we use the current CPU write domain rather than moving the object to the GTT domain for the purposes of the pwrite. This has the advantage of not flushing the presumably hot data that we want to upload into the bo, and of ascribing the clflush to the execution when profiling. Signed-off-by:
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Chris Wilson authored
The callers expect us to cleanup any partially initialised structures before reporting the error. Signed-off-by:
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Chris Wilson authored
If the object is bigger than the entire aperture, reject it early before evicting everything in a vain attempt to find space. v2: Use E2BIG as suggested by Owain G. Ainsworth. Signed-off-by:
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Chris Wilson authored
Signed-off-by:
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Chris Wilson authored
This particular warning is harmless as we emit during the normal pinning process where the batch buffer requires more fences than is available without eviction. Only if we fail to evict enough fences does this become a problem, so include the requested number of fences in the ultimate *error* message. v2: Remember to compile test even trial patches to remove warnings. Signed-off-by:
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Chris Wilson authored
Whilst pinning the buffer, check that that its current alignment matches the requested alignment. If it does not, rebind. This should clear up any final render errors whilst resuming, for reference: Bug 27070 - [i915] Page table errors with empty ringbuffer https://bugs.freedesktop.org/show_bug.cgi?id=27070 Bug 15502 - render error detected, EIR: 0x00000010 https://bugzilla.kernel.org/show_bug.cgi?id=15502 Bug 13844 - i915 error: "render error detected" https://bugzilla.kernel.org/show_bug.cgi?id=13844Signed-off-by:
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Chris Wilson authored
Add the pitch that we about to write into the control register along with the base, offset and coordinates that go into the other control registers. Signed-off-by:
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Chris Wilson authored
If the FBC is already disabled, then we do not even attempt to disable FBC and so there is no point emitting a debug statement at that point, having already emitted one saying why we are disabling FBC. Signed-off-by:
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Chris Wilson authored
Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Chris Wilson authored
Nesting domain changes will cause confusion when trying to interpret the tracepoints describing the sequence of changes for the object, as well as obscuring the order of operations for the reader of the code. Signed-off-by:
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Chris Wilson authored
Delay taking the mutex until we need to and ensure that we hold the spinlock when resetting unpin_work on the error path. Also defer the debugging print messages until after we have released the spinlock. Signed-off-by:
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Chris Wilson authored
Only report an error if the GPU has actually detected one, otherwise we are just hung. Signed-off-by:
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- 26 May, 2010 23 commits
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Eric Anholt authored
Fixes /debug/dri/0/i915_gem_interrupt output for status page. Signed-off-by: -
Li Peng authored
Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by:
Li Peng <peng.li@intel.com> Signed-off-by:
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Dan Carpenter authored
The "encoder" variable can never be null because it is used as loop cursor in a list_for_each_entry() loop. Signed-off-by:
Dan Carpenter <error27@gmail.com> Signed-off-by:
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Dan Carpenter authored
The "connector" variable is used as the cursor in a list_for_each_entry() and it's always non-null so we don't need to check it. Signed-off-by:
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Zhenyu Wang authored
For real HDMI sink, CPT HDMI port has to set 'HDMI' mode flag in order to make HDMI audio work correctly. This is required patch for drm/i915 to enable HDMI audio on CPT PCH, ALSA patch is at http://mailman.alsa-project.org/pipermail/alsa-devel/2010-May/027601.htmlTested-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Daniel Vetter authored
This saves a whooping 7 dwords. Zero functional changes. Because some of the refcounts are rather tightly calculated, I've put BUG_ONs in the code to check for overflows. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Adam Jackson authored
Signed-off-by:
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Adam Jackson authored
DisplayPort spec v1.1a, Table 2-52. Signed-off-by:
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Chris Wilson authored
We can, by virtue of a vblank interrupt firing in the middle of setting up the unpin work (i.e. after we set the unpin_work field and before we write to the ringbuffer) enter intel_finish_page_flip() prior to receiving the pending flip notification. Therefore we can expect to hit intel_finish_page_flip() under normal circumstances without a pending flip and even without installing the pending_flip_obj. This is exacerbated by aperture thrashing whilst binding the framebuffer References: Bug 28079 - "glresize" causes kernel panic in intel_finish_page_flip. https://bugs.freedesktop.org/show_bug.cgi?id=28079Reported-by:
Nick Bowler <nbowler@draconx.ca> Signed-off-by:
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Chris Wilson authored
References: Bug 15733 - Crash when accessing nonexistent GTT entries in i915 https://bugzilla.kernel.org/show_bug.cgi?id=15733 On G33 and above, the size of the GTT space is determined by the GMCH control register. Prior to this revision, the size is determined by the size of the aperture. So we must careful to map and fill the appropriate range depending on chipset. Signed-off-by:
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Tobias Klauser authored
The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by:
Tobias Klauser <tklauser@distanz.ch> Signed-off-by:
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Jesse Barnes authored
Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by:
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Adam Jackson authored
Disable the CRT plug interrupt while doing the force cycle, explicitly clear any CRT interrupt we may have generated, and restore when done. Should mitigate interrupt storms from hotplug detection. Signed-off-by:
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Krzysztof Halasa authored
This doesn't change the clock limits (minimums), i.e. it won't make it output 720x576 PAL nor 720x480 NTSC, but it will work with modes like 1080i etc. (including GLX and textured Xvideo, not sure about the overlay). Tested on i915 + analog VGA, it would be worth checking if newer chips (and which ones) still support interlaced mode. Signed-off-by:
Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by:
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Daniel J Blueman authored
While investigating Intel i5 Arrandale GPU lockups with -rc4, I noticed a lock imbalance. Signed-off-by:
Daniel J Blueman <daniel.blueman@gmail.com> Signed-off-by:
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Li Zefan authored
Convert i915_gem_object_clflush to DEFINE_EVENT, and save ~0.5K: text data bss dec hex filename 13204 2732 12 15948 3e4c i915_trace_points.o.orig 12668 2732 12 15412 3c34 i915_trace_points.o No change in functionality. Signed-off-by:
Li Zefan <lizf@cn.fujitsu.com> Acked-by:
Steven Rostedt <rostedt@goodmis.org> Signed-off-by:
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Jesse Barnes authored
FBC disable on 965 can take long enough to trigger latency checks in the kernel so be sure to timeout after a reasonable period. Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15015. Tested-by:
James Ettle <theholyettlz@googlemail.com> Signed-off-by:
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Zou Nan hai authored
The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by:
Zou Nan hai <nanhai.zou@intel.com> Signed-off-by:
Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by:
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Zou Nan hai authored
The active list and request list move into the ringbuffer structure, so each can track its active objects in the order they are in that ring. The flushing list does not, as it doesn't matter which ring caused data to end up in the render cache. Objects gain a pointer to the ring they are active on (if any). Signed-off-by:
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Zou Nan hai authored
Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by:
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Eric Anholt authored
With the advent of the BSD ring, be clear about which ring this is. The docs are pretty consistent with calling this the Render engine at this point.
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Eric Anholt authored
This is preparation for supporting multiple ringbuffers on Ironlake. The non-copy-and-paste changes are: - de-staticing functions - I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files. - i915_gem_add_request had only half its implementation copy-and-pasted out of the middle of it.
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Chris Wilson authored
The i915's implementation of KMS requires GEM in order to manage the memory and execution domains of the framebuffer and associated resources. By the point at which we detect broken a BIOS and need to disable GEM, we have already registered ourselves as a KMS driver with several subsystems. Rather than introducing a fragile unwind and attempt to continue with UMS, spit out an error and unload the driver. References: [Bug 15754] IP: [<ffffffffa0207589>] drm_mm_search_free+0x49/0x90 [drm] BUG: unable to handle kernel NULL pointer dereference at (null) https://bugzilla.kernel.org/show_bug.cgi?id=15754 [drm:i915_driver_load] *ERROR* Detected broken video BIOS with 262140/262144kB of video memory stolen. [drm:i915_driver_load] *ERROR* Disabling GEM. (try reducing stolen memory or updating the BIOS to fix). i915 0000:00:02.0: irq 30 for MSI/MSI-X [drm] set up 255M of stolen space BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<ffffffffa0207589>] drm_mm_search_free+0x49/0x90 [drm] PGD 69719067 PUD 69dda067 PMD 0 Oops: 0000 [#1] PREEMPT SMP last sysfs file: /sys/module/snd_seq_oss/initstate CPU 1 Pid: 867, comm: modprobe Not tainted 2.6.33-ARCH #1 G43Twins-FullHD/To Be Filled By O.E.M. RIP: 0010:[<ffffffffa0207589>] [<ffffffffa0207589>] drm_mm_search_free+0x49/0x90 [drm] RSP: 0018:ffff8800699f3af8 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffffffffffffffff RCX: 0000000000000000 RDX: 0000000000001000 RSI: 0000000000001000 RDI: ffff8800693d0f78 RBP: ffff8800699f3b18 R08: 0000000000001000 R09: 0000000000000000 R10: 2222222222222222 R11: 0000000000000000 R12: ffff880068de70c0 R13: 0000000000001000 R14: 0000000000000000 R15: ffff8800689cb000 FS: 00007fa93f4e5700(0000) GS:ffff880001880000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000000695a0000 CR4: 00000000000406e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process modprobe (pid: 867, threadinfo ffff8800699f2000, task ffff8800694f4740) Stack: ffff880068de73c0 ffff880068de70c0 ffff8800689cb000 0000000000001000 <0> ffff8800699f3b68 ffffffffa0299f63 ffff8800693d0f78 0000120068de70c0 <0> ffff8800689cb000 ffff880068de73c0 ffff880068de70c0 ffff8800689cb000 Call Trace: [<ffffffffa0299f63>] i915_gem_object_bind_to_gtt+0x83/0x360 [i915] [<ffffffffa029a2e5>] i915_gem_object_pin+0xa5/0xb0 [i915] [<ffffffffa029a3c5>] i915_gem_init_ringbuffer+0xd5/0x510 [i915] [<ffffffffa028dbee>] i915_driver_load+0x4ce/0xd00 [i915] [<ffffffffa0205d37>] ? drm_sysfs_device_add+0x87/0xb0 [drm] [<ffffffffa0203363>] ? drm_get_minor+0x1d3/0x330 [drm] [<ffffffffa02037e6>] drm_get_dev+0x326/0x580 [drm] [<ffffffffa02bc0a5>] i915_pci_probe+0x10/0xd0 [i915] [<ffffffff811e98a2>] local_pci_probe+0x12/0x20 [<ffffffff811ea8e0>] pci_device_probe+0x80/0xb0 [<ffffffff8127b12a>] ? driver_sysfs_add+0x5a/0x90 [<ffffffff8127b273>] driver_probe_device+0x93/0x1a0 [<ffffffff8127b413>] __driver_attach+0x93/0xa0 [<ffffffff8127b380>] ? __driver_attach+0x0/0xa0 [<ffffffff8127a8f8>] bus_for_each_dev+0x68/0x90 [<ffffffff8127b0c9>] driver_attach+0x19/0x20 [<ffffffff8127a0ad>] bus_add_driver+0xcd/0x2d0 [<ffffffff8127b718>] driver_register+0x78/0x140 [<ffffffff811eab91>] __pci_register_driver+0x51/0xd0 [<ffffffffa02d6000>] ? i915_init+0x0/0x52 [i915] [<ffffffffa01fdc31>] drm_init+0x111/0x120 [drm] [<ffffffff810eb0cd>] ? register_shrinker+0x4d/0x60 [<ffffffffa02d6000>] ? i915_init+0x0/0x52 [i915] [<ffffffffa02d6050>] i915_init+0x50/0x52 [i915] [<ffffffff81002047>] do_one_initcall+0x37/0x1a0 [<ffffffff8108ed17>] sys_init_module+0xd7/0x250 [<ffffffff81009fc2>] system_call_fastpath+0x16/0x1b Code: eb 29 49 8b 41 28 31 d2 49 f7 f5 85 d2 74 39 44 89 c0 29 d0 48 89 c2 48 01 f2 49 39 d2 73 29 0f 1f 00 49 89 da 4c 89 d3 4d 89 d9 <4d> 8b 19 49 39 f9 41 0f 18 0b 74 2b 4d 8b 51 30 4d 89 cc 49 39 RIP [<ffffffffa0207589>] drm_mm_search_free+0x49/0x90 [drm] RSP <ffff8800699f3af8> CR2: 0000000000000000 Signed-off-by:
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