1. 24 Apr, 2024 6 commits
    • Arınç ÜNAL's avatar
      net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, add MT7531_QRY_FFP · 9c7401dc
      Arınç ÜNAL authored
      The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
      SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
      MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
      IGMP/MLD Query Frame Flooding Ports mask for MT7531.
      
      Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
      
      Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
      macros.
      Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9c7401dc
    • Arınç ÜNAL's avatar
      net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to mt753x_to_cpu_fw · 7603a0c7
      Arınç ÜNAL authored
      The mt753x_bpdu_port_fw enum is globally used for manipulating the process
      of deciding the forwardable ports, specifically concerning the CPU port(s).
      Therefore, rename it and the values in it to mt753x_to_cpu_fw.
      
      Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
      Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7603a0c7
    • Arınç ÜNAL's avatar
      net: dsa: mt7530: rename p5_intf_sel and use only for MT7530 switch · eeaf9acb
      Arınç ÜNAL authored
      The p5_intf_sel pointer is used to store the information of whether PHY
      muxing is used or not. PHY muxing is a feature specific to port 5 of the
      MT7530 switch. Do not use it for other switch models.
      
      Rename the pointer to p5_mode to store the mode the port is being used in.
      Rename the p5_interface_select enum to mt7530_p5_mode, the string
      representation to mt7530_p5_mode_str, and the enum elements.
      
      If PHY muxing is not detected, the default mode, GMAC5, will be used.
      Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      eeaf9acb
    • Arınç ÜNAL's avatar
      net: dsa: mt7530: refactor MT7530_PMCR_P() · 883ea1c0
      Arınç ÜNAL authored
      The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
      MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
      for MT7530 only. Add MT7530 prefix to the definition for bit 15.
      
      Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
      
      Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
      follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
      "MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
      Generation Router Platform: Datasheet (Open Version) v0.1" documents.
      
      These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
      with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
      
      Remove PMCR_SPEED_MASK which doesn't have a use.
      
      Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
      end for the mask that includes all force mode definitions.
      Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      883ea1c0
    • Arınç ÜNAL's avatar
      net: dsa: mt7530: disable EEE abilities on failure on MT7531 and MT7988 · 385c22ee
      Arınç ÜNAL authored
      The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the
      PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE
      abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are
      unset, the abilities are left to be determined by PHY auto polling.
      
      The commit 40b5d2f1 ("net: dsa: mt7530: Add support for EEE features")
      made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on
      mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and
      MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be
      determined by PHY auto polling, regardless of the result of phy_init_eee().
      
      Define these bits and add them to the MT7531_FORCE_MODE mask which is set
      in mt7531_setup_common(). With this, there won't be any EEE abilities set
      when phy_init_eee() returns a negative value.
      
      Thanks to Russell for explaining when phy_init_eee() could return a
      negative value below.
      
      Looking at phy_init_eee(), it could return a negative value when:
      
      1. phydev->drv is NULL
      2. if genphy_c45_eee_is_active() returns negative
      3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT
      4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY)
      
      If we then look at genphy_c45_eee_is_active(), then:
      
      genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their
      non-zero return values, otherwise this function returns zero or positive
      integer.
      
      If we then look at genphy_c45_read_eee_adv(), then a failure of
      phy_read_mmd() would cause a negative value to be returned.
      
      Looking at genphy_c45_read_eee_lpa(), the same is true.
      
      So, it can be summarised as:
      
      - phydev->drv is NULL
      - there is a communication error accessing the PHY
      - EEE is not active
      
      otherwise, it returns zero on success.
      
      If one wishes to determine whether an error occurred vs EEE not being
      supported through negotiation for the negotiated speed, if it returns
      -EPROTONOSUPPORT in the latter case. Other error codes mean either the
      driver has been unloaded or communication error.
      
      In conclusion, determining the EEE abilities by PHY auto polling shouldn't
      result in having any EEE abilities enabled, when one of the last two
      situations in the summary happens. And it seems that if phydev->drv is
      NULL, there would be bigger problems with the device than a broken link. So
      this is not a bugfix.
      Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      385c22ee
    • Eric Dumazet's avatar
      neighbour: fix neigh_master_filtered() · 1c04b46c
      Eric Dumazet authored
      If we no longer hold RTNL, we must use netdev_master_upper_dev_get_rcu()
      instead of netdev_master_upper_dev_get().
      
      Fixes: ba0f7806 ("neighbour: no longer hold RTNL in neigh_dump_info()")
      Signed-off-by: default avatarEric Dumazet <edumazet@google.com>
      Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
      Link: https://lore.kernel.org/r/20240421185753.1808077-1-edumazet@google.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      1c04b46c
  2. 23 Apr, 2024 34 commits