- 30 Mar, 2017 40 commits
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Monk Liu authored
set bit 21 of IB.control filed to actually enable MCBP for SRIOV v2: add flag for preemption enable bit for soc15 and use this flag instead of hardcode. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Monk Liu authored
when MCBP enabled for gfx8, the cond_exec must also be implemented, otherwise there will be odds to meet cross engine (ce and me) deadlock when world switch happens. Signed-off-by:
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Monk Liu authored
1,the check is only appliable for SRIOV GFX engine. 2,use chunk_ib instead of ib. Signed-off-by:
Ken Wang <Qingqing.wang@amd.com> Signed-off-by:
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Monk Liu authored
to prevent submit two or more IBs with PREEMPT flags. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
should use chunk_ib instead of ib, otherwise the logic is incorrect. Signed-off-by:
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Nicolai Hähnle authored
Also, add the fence of the clear operations to the BO to ensure that the underlying memory can only be re-used after all PTEs pointing to it have been cleared. This avoids the following sequence of events that could be triggered by user space: 1. Submit a CS that accesses some BO _without_ adding that BO to the buffer list. 2. Free that BO. 3. Some other task re-uses the memory underlying the BO. 4. The CS is submitted to the hardware and accesses memory that is now already in use by somebody else. By clearing the page tables immediately in step 2, a GPU VM fault will be triggered in step 4 instead of wild memory accesses. v2: use amdgpu_bo_fence directly Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
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Christian König authored
Allocate and free page directories on demand. V2: a. clear entries allocation b. fix entries index calculation c. need alloc sub level even parent bo was allocated Signed-off-by: Christian König <christian.koenig@amd.com> (v1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (v2) Acked-by: Alex Deucher <alexander.deucher@amd.com> (v2) Signed-off-by: -
Christian König authored
Not the best solution, but good enough for now. Signed-off-by:
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Christian König authored
Update all levels of the page directory. V2: a. sub level pdes always are written to incorrect place. b. sub levels need to update regardless of parent updates. Signed-off-by: Christian König <christian.koenig@amd.com> (V1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (V1) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (V2) Acked-by: Alex Deucher <alexander.deucher@amd.com> (V2) Signed-off-by: -
Christian König authored
Move all levels to the end after command submission. Signed-off-by:
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Christian König authored
All page directory levels should be in place after this. Signed-off-by:
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Christian König authored
Allows us to get the size for all levels as well. v2: agd: fix warning Signed-off-by:
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Christian König authored
No functional change, but the base for multi level page tables. Signed-off-by:
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Christian König authored
Needs to be filled with handling. Signed-off-by:
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Christian König authored
This way we save passing it through the different functions. Signed-off-by:
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Christian König authored
Decribes better what this is used for. Signed-off-by:
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Rex Zhu authored
for power readings. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Huang Rui authored
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Huang Rui authored
v2: squash register typo fix from Ray v3: fix spelling Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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Alex Deucher authored
The ring structure already has what we need. Reviewed-by:
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Alex Deucher authored
Avoids passing around additional parameters during setup. Reviewed-by:
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Alex Deucher authored
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by:
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Alex Deucher authored
It's required. Reviewed-by:
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Alex Deucher authored
It's required. Reviewed-by:
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Alex Deucher authored
To better match where they are used. Called from sw_init and sw_fini. Reviewed-by:
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Alex Deucher authored
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Xiangliang Yu authored
For MM sriov, need use MMSCH to init engine and the init procedures are all saved in mm table. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
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Xiangliang Yu authored
For MM SRIOV, need to prepare MM table send send it to MMSCH to initial UVD & VCE engine. Create new header file for the structures. Signed-off-by:
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Xiangliang Yu authored
In order to not break SRIOV gfx development, will revert this patch after vce proved working. Signed-off-by:
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Xiangliang Yu authored
Allocate MM table for sriov device. Signed-off-by:
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Xiangliang Yu authored
Add new structure for MM table for multi media scheduler of sriov. Signed-off-by:
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