- 31 Dec, 2021 4 commits
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Miquel Raynal authored
Raw NAND core: * Export nand_read_page_hwecc_oob_first() GPMC memory controller for OMAP2 NAND controller: * GPMC: - Add support for AM64 SoC and allow build on K3 platforms - Use a compatible match table when checking for NAND controller - Use platform_get_irq() to get the interrupt Raw NAND controller drivers: * OMAP2 NAND controller: - Document the missing 'rb-gpios' DT property - Drop unused variable - Fix force_8bit flag behaviour for DMA mode - Move to exec_op interface - Use platform_get_irq() to get the interrupt * Renesas: - Add new NAND controller driver with its bindings and MAINTAINERS entry * Onenand: - Remove redundant variable ooblen * MPC5121: - Remove unused variable in ads5121_select_chip() * GPMI: - Add ERR007117 protection for nfc_apply_timings - Remove explicit default gpmi clock setting for i.MX6 - Use platform_get_irq_byname() to get the interrupt - Remove unneeded variable * Ingenic: - JZ4740 needs 'oob_first' read page function * Davinci: - Rewrite function description - Avoid duplicated page read - Don't calculate ECC when reading page Signed-off-by:Miquel Raynal <miquel.raynal@bootlin.com>
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Miquel Raynal authored
SPI NOR core changes: - Add Pratyush as SPI NOR co-maintainer. - Flash parameters initialization was done in a spaghetti way. Clean flash parameters initialization. - Rework the flash_info flags and clarify where one should be used. - Initialize all flash parameters based on JESD216 SFDP where possible. Flash parameters and settings that are SFDP discoverable should not be duplicated via flash_info flags at flash declaration. - Remove debugfs entries that duplicate sysfs entries. SPI NOR manufacturer drivers changes: - Use late_init() hook in various drivers to make it clear that those flash parameters are either not declared in the JESD216 SFDP standard, or the SFDP tables which define those flash parameters are not defined by the flash. - Fix mtd size for s3an flashes. - Write 2 bytes when disabling Octal DTR mode: 1 byte long transactions are not allowed in 8D-8D-8D mode. Signed-off-by: -
Miquel Raynal authored
Hyperbus changes for v5.17-rc1 Hyperbus changes: Couple of fixes in Renesas hyperbus rpc-if driver to avoid crash on module remove and for missing check for error value in probe. Signed-off-by: -
Miquel Raynal authored
Memory controller drivers for v5.17 - OMAP GPMC 1. Add support for AM64 SoC. 2. Minor improvement: use platform_get_irq(). [miquel.raynal@bootlin.com: A first commit introduced a new omap compatible and another moved the IDs to a header which created a conflict: moving the new ID as well in the header fixed it.] Signed-off-by:
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- 29 Dec, 2021 1 commit
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Tudor Ambarus authored
SPI NOR sysfs defines partname and jedec_id device attributes, which duplicate the information from debugfs. Since the sysfs directory structure and the attributes in each directory define an ABI between the kernel and user space, thus it can never be removed, remove the debugfs entries so that we don't duplicate the information. Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by:
Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211217122636.474976-2-tudor.ambarus@microchip.com
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- 23 Dec, 2021 5 commits
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Pratyush Yadav authored
The Octal DTR configuration is stored in the CFR0V register. This register is 1 byte wide. But 1 byte long transactions are not allowed in 8D-8D-8D mode. The next byte address contains the CFR1V register, which contains the number of dummy cycles. This is very fortunate since the enable path changes the value of this register. Reset the value to its default when disabling Octal DTR mode. This way, both changes to the flash state made when enabling can be reverted in one single transaction. Signed-off-by:
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Pratyush Yadav authored
The Octal DTR configuration is stored in the CFR5V register. This register is 1 byte wide. But 1 byte long transactions are not allowed in 8D-8D-8D mode. Since the next byte address does not contain any register, it is safe to write any value to it. Write a 0 to it. Signed-off-by:
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Pratyush Yadav authored
The template ops used in spi_nor_spimem_check_pp() and spi_nor_spimem_check_readop() currently set the data phase to 1 byte long. This is problematic for 8D-8D-8D protocol where odd length data phase is invalid since one cycle transfers 2 bytes and odd number of bytes would mean half a cycle is left over. This could result in a controller rejecting the op as "not supported" even though it actually supports the protocol. Change the data length to 2 bytes in these templates. One might argue that this should only be done for 8D-8D-8D operations but when talking about these templates, there is no functional difference between one and two bytes, even in STR modes. Signed-off-by:
Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20210531181757.19458-2-p.yadav@ti.com
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Tudor Ambarus authored
Constify 'struct spi_nor_fixups' in order to respect flash_info structure declaration. Signed-off-by:
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Flavio Suligoi authored
Remove the references to the old spi-nor.c file. The old drivers/mtd/spi-nor/spi-nor.c file is not more present and now some of its code is contained in: drivers/mtd/spi-nor/core.c Signed-off-by:
Flavio Suligoi <f.suligoi@asem.it> [tudor.ambarus@microchip.com: - remove change in Documentation/driver-api/mtd/spi-nor.rst. The documentation has to be rewritten entirely. - update commit message] Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20210126092516.1431913-1-f.suligoi@asem.it
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- 22 Dec, 2021 7 commits
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Lad Prabhakar authored
platform_get_resource_byname(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_byname(). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by:
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Roger Quadros authored
The GPMC device driver is required for NAND controller to work on K3 Architecture. Select it if required. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Roger Quadros authored
As more compatibles can be added to the GPMC NAND controller driver use a compatible match table. Signed-off-by:
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Roger Quadros authored
The TI's AM64 SoC has the GPMC module. Add compatible for it. Traditionally GPMC external addresses have always been mapped to first 1GB physical address. However newer platforms, can have it mapped at different locations. Support this address provision via device tree. Signed-off-by:
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Roger Quadros authored
AM64 SoC contains the GPMC module. Add compatible for it. Newer SoCs don't necessarily map GPMC data region at the same place as legacy SoCs. Add reg-names "data", to provide this information to the device driver. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211221131757.2030-2-rogerq@kernel.orgSigned-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by:
Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20211221203916.18588-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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- 21 Dec, 2021 3 commits
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Miquel Raynal authored
Point to the driver and the bindings. Signed-off-by:
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Miquel Raynal authored
Introduce Renesas NAND controller driver which currently supports the following features on R-Car Gen3 and RZ/N1 SoCs: - All ONFI timing modes - Different configurations of its internal ECC controller - On-die (not tested) and software ECC support - Several chips (not tested) - Subpage accesses - DMA and PIO This controller was originally provided by Evatronix before being bought by Cadence. Signed-off-by:
Ralph Siemsen <ralph.siemsen@linaro.org> Acked-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/linux-mtd/20211217142033.353599-3-miquel.raynal@bootlin.com
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Miquel Raynal authored
Add a Yaml description for this Renesas NAND controller. As this controller is embedded on different SoC families, provide: * a family-specific "r-car-gen3" compatible and a more specific "r8a77951" one * a family-specific "rzn1" compatible and a more specific "r9a06g032" one More compatibles can be added later if new SoCs with this controller must be supported. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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- 17 Dec, 2021 7 commits
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Minghao Chi authored
Return status directly from function called. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by:
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Roger Quadros authored
devsize is not used anywhere in code. Drop it. Signed-off-by:
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Roger Quadros authored
In DMA mode we were not considering the force_8bit flag. Fix it by using regular non-DMA 8-bit I/O if force_8bit flag is set. Signed-off-by:
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Roger Quadros authored
AM64 SoC contains the GPMC NAND controller. Add compatible for it. Signed-off-by:
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Roger Quadros authored
Stop using legacy interface and move to the exec_op interface. Signed-off-by:
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Roger Quadros authored
K3 platforms come with GPMC. Enable GPMC build for K3 platforms. Signed-off-by:
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Roger Quadros authored
AM64 SoC contains the GPMC NAND controller. Add compatible for it. Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by:
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- 09 Dec, 2021 5 commits
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Michał Kępień authored
In the mtdchar_write_ioctl() function, memdup_user() is called with its 'len' parameter set to verbatim values provided by user space via a struct mtd_write_req. Both the 'len' and 'ooblen' fields of that structure are 64-bit unsigned integers, which means the MEMWRITE ioctl can trigger unbounded kernel memory allocation requests. Fix by iterating over the buffers provided by user space in a loop, processing at most mtd->erasesize bytes in each iteration. Adopt some checks from mtd_check_oob_ops() to retain backward user space compatibility. Suggested-by:
Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by:
Michał Kępień <kernel@kempniu.pl> Signed-off-by:
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Christophe JAILLET authored
'chip_map' is a bitmap. So use 'bitmap_zalloc()' to simplify code, improve the semantic and avoid some open-coded arithmetic in allocator arguments. Also change the corresponding 'kfree()' into 'bitmap_free()' to keep consistency. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Miquel Raynal authored
When developping NAND controller drivers or when debugging filesystem corruptions, it is quite common to need hacking locally into the MTD/NAND core in order to get access to the content of the bad blocks. Instead of having multiple implementations out there let's provide a simple yet effective specific MTD-wide debugfs entry to fully disable these checks on purpose. A warning is added to inform the user when this mode gets enabled. Signed-off-by:
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Rob Herring authored
With 'unevaluatedProperties' support implemented, the TI GPMC example has a warning: Documentation/devicetree/bindings/memory-controllers/ti,gpmc.example.dt.yaml: nand@0,0: Unevaluated properties are not allowed ('rb-gpios' was unexpected) Add the missing definition for 'rb-gpios'. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Roger Quadros <rogerq@kernel.org> Cc: linux-mtd@lists.infradead.org Signed-off-by:Thierry Reding <treding@nvidia.com> Reviewed-by:
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Colin Ian King authored
Variable ooblen is being initialized with a value that is never read. The variable is never used after this, so it is redundant and can be removed. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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- 07 Dec, 2021 8 commits
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Tudor Ambarus authored
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4_4B 0xec, for erases SPINOR_OP_BE_4K_4B 0x21, and for writes SPINOR_OP_PP_4B 0x12. Signed-off-by:
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Tudor Ambarus authored
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4_4B 0xec, for erases SPINOR_OP_BE_4K_4B 0x21, and for writes SPINOR_OP_PP_1_1_4_4B 0x34. Signed-off-by:
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Tudor Ambarus authored
s25fl256s0 does not define the SFDP tables nor implements the RDSFDP 0x5a command. Skip the SFDP parsing in order to avoid issuing an unsupported command to the flash. Signed-off-by:
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Tudor Ambarus authored
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4 0xeb, for erases SPINOR_OP_BE_4K 0x20, and for writes SPINOR_OP_PP 0x02. Signed-off-by:
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Tudor Ambarus authored
spi_nor_setup() configures the SPI NOR memory. Setting the addr width is too a configuration, hence we can move the spi_nor_set_addr_width() in spi_nor_setup(). Signed-off-by:
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Tudor Ambarus authored
New flash additions that support SFDP should be declared with PARSE_SFDP and with all the other flags that are not SFDP discoverable. Keep the old way of initializing the flash, until all the flashes are converted to use either PARSE_SFDP or SPI_NOR_SKIP_SFDP. Flashes that declare PARSE_SFDP do not have a roll-back mechanism because if spi_nor_parse_sfdp() returns an error it means that either BFPT is not supported, thus SFDP is not supported and the user didn't correctly declared the flash_info entry, or some memalloc failed. Either way we should return an error. The rest of the SFDP tables are optional, if one of the optional SFDP tables fails, we just continue. We would like to get rid of the default_init() hook, so the spi_nor_manufacturer_init_params() is not called in the new sequnce of flash initialization. Split spi_nor_info_init_params() in spi_nor_init_default_params() and spi_nor_no_sfdp_init_params(). spi_nor_init_default_params() is called for all the flashes regardless if they support SFDP or not. spi_nor_no_sfdp_init_params() is called just for the flashes that do not define SFDP and initializes parameters and setting solely based on flash_info data. Signed-off-by:
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Tudor Ambarus authored
Group NOR flags initialization. Introduce a dedicated function for setting the fixup_flags and emphasise when those flash_info flags should be set: when the SNOR_F_4B_OPCODES/SNOR_F_IO_MODE_EN_VOLATILE setttings can not be discovered by SFDP for this particular flash because the SFDP table that indicates this support is not defined in the flash. In case the table for his support is defined but has wrong values, one should instead use a post_sfdp() hook to set the SNOR_F equivalent flag. No functional change intended in this patch. Signed-off-by:
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Tudor Ambarus authored
Used to initialize the NOR flags for settings that are not defined in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP. This moves the setting of SNOR_F_READY_XSR_RDY and SNOR_F_HAS_LOCK late in the init call, without any functional change expected. The rest of the flags were already set after the spi_nor_init_params(). Signed-off-by:
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