- 27 Sep, 2022 13 commits
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Dmitry Baryshkov authored
PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-3-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
Add device tree bindings for the display clock controller on Qualcomm SM8450 platform. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Adam Skladowski authored
Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Signed-off-by:
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Adam Skladowski authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6115 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> [bjorn: Minor fix of binding description] Signed-off-by:
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Krishna chaitanya chundru authored
Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by:
Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by:
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Satya Priya authored
Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe() to avoid remapping of memory region for index 0, which is already being done through qcom_cc_map(). Fixes: 7c6a6641 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280") Signed-off-by:
Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by:
Neil Armstrong <neil.armstrong@baylibre.com> Signed-off-by:
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Robert Marko authored
Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Update the IPQ6018 Alpha PLL config to the latest one from the downstream 5.4 kernel[1]. This one should match the production SoC-s. Tested on IPQ6018 CP01-C1 reference board. [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41Signed-off-by:
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Robert Marko authored
Convert the driver to use OF match data for providing the Alpha PLL config per compatible. This is required for IPQ8074 support since it uses a different Alpha PLL config. While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make it clear that it is for IPQ6018 only. Signed-off-by:
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Robert Marko authored
Add IPQ8074 compatible to A53 PLL bindings. Signed-off-by:
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Robert Marko authored
While fixing up the driver I noticed that my IPQ8074 board was hanging after CPUFreq switched the frequency during boot, WDT would eventually reset it. So mark apcs_alias0_core_clk as critical since its the clock feeding the CPU cluster and must never be disabled. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by:
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Robert Marko authored
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is currently broken. More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux clock. However after debugging why it was always stuck at 800Mhz, it was figured out that its not regmap_mux compatible at all. It is a simple mux but it uses RCG2 register layout and control bits, so utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not having to provide a dummy frequency table. While we are here, use ARRAY_SIZE for number of parents. Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by:
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Christian Marangi authored
An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
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- 26 Sep, 2022 15 commits
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Christian Marangi authored
Use ARRAY_SIZE for num_parents instead of raw number to prevent any confusion/mistake. Signed-off-by:
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Christian Marangi authored
Convert lcc-ipq806x driver to parent_data API. Change parent_name for pll4 to pxo_board to prepare the future to eventually drop the double pxo board clk. Signed-off-by:
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Christian Marangi authored
Add reset definition for lcc-ipq806x. Signed-off-by:
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Christian Marangi authored
Add pcm reset define for ipq806x lcc. Signed-off-by:
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Dmitry Baryshkov authored
Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by:
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Dmitry Baryshkov authored
Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by:
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Dmitry Baryshkov authored
Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by:
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Dmitry Baryshkov authored
To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by:
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Yassine Oudjana authored
Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> [DB: switch to parent_hws for pmux clocks] Signed-off-by:
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Yassine Oudjana authored
The clocks currently listed in clocks and clock-names are the ones supplied by this clock controller, not the ones it consumes. Replace them with the only clock it consumes - the on-board oscillator (XO), and make the properties required. Signed-off-by:
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Yassine Oudjana authored
There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by:
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Yassine Oudjana authored
The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by:
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Yassine Oudjana authored
This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by:
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Yassine Oudjana authored
The parent at this index is the secondary mux, which can connect not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX to better reflect the parent. Signed-off-by:
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- 14 Sep, 2022 12 commits
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Stephan Gerhold authored
MSM8909 has mostly the same as clocks in RPM as MSM8916, but additionally the QPIC clock for the NAND flash controller. Signed-off-by:
Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by:
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Stephan Gerhold authored
Document the "qcom,rpmcc-msm8909" compatible for the clocks available via the RPM on the MSM8909 SoC. Signed-off-by:
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Stephan Gerhold authored
The USB PHY on MSM8909 works with the driver used on MSM8916 (phy-qcom-usb-hs.c). When turning the PHY on/off it is first reset using the standard reset controller API. On MSM8916 the reset is provided by the USB driver (ci_hdrc_msm_por_reset() in ci_hdrc_msm.c). While this seems to work on MSM8909 as well, the Qualcomm Linux sources suggest that the PHY should be reset using the GCC_USB2_HS_PHY_ONLY_BCR register instead. In general this is easy to set up in the device tree, thanks to the standard reset controller API. However, to conform to the specifications of the PHY the reset signal should be asserted for at least 10 us. This is handled correctly on MSM8916 in ci_hdrc_msm_por_reset(), but not within the GCC driver. Fix this by making use of the new "udelay" field of qcom_reset_map and set a delay of ~15 us between the assertion/deassertion of the USB PHY reset signal. Signed-off-by:
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Stephan Gerhold authored
The amount of time required between asserting and deasserting the reset signal can vary depending on the involved hardware component. Sometimes 1 us might not be enough and a larger delay is necessary to conform to the specifications. Usually this is worked around in the consuming drivers, by replacing reset_control_reset() with a sequence of reset_control_assert(), waiting for a custom delay, followed by reset_control_deassert(). However, in some cases the driver making use of the reset is generic and can be used with different reset controllers. In this case the reset time requirement is better handled directly by the reset controller driver. Make this possible by adding an "udelay" field to the qcom_reset_map that allows setting a different reset delay (in microseconds). Signed-off-by:
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Stephan Gerhold authored
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a driver for it to make it possible to enable additional functionality for the SoC. Work on this driver was originally started independently by Dominik, I picked it up and added missing clocks/resets, as well as various cleanup to bring it into shape for mainline. Co-developed-by:
Dominik Kobinski <dominikkobinski314@gmail.com> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Stephan Gerhold authored
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a DT schema to describe it, similar to other Qualcomm SoCs. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s clocks. This simplifies the driver and removes extra code duplication. The clock mi2s_div_clk used .enable_reg/.enable_bit, however these fields are not used with by the clk_regmap_div_ops, thus they are silently dropped. Clock enablement is handled in the mi2s_bit_div_clk clock. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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