- 27 Mar, 2020 1 commit
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yong mao authored
SDIO irq is not triggered by low level, but by falling edge in our previous IC. This mechanism only have one chance to catch the SDIO irq if a SDIO irq comes within the multiple block transmission. This SDIO irq may be easily lost, because falling edge appears only once within 2 clock after data transmission is completed. SDIO irq recheck mechanism will make sure all irqs can be processed correctly. Signed-off-by:
Yong Mao <yong.mao@mediatek.com> Link: https://lore.kernel.org/r/1585299097-6897-2-git-send-email-yong.mao@mediatek.comSigned-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 26 Mar, 2020 3 commits
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Ludovic Barre authored
The busyd0 line transition can be very fast. The busy request may be completed by busy_d0end, without waiting for the busy_d0 steps. Therefore, clear the busyd0end irq flag, even if no busy_status. Fixes: 0e68de6a ("mmc: mmci: sdmmc: add busy_complete callback") Cc: stable@vger.kernel.org Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Link: https://lore.kernel.org/r/20200325143409.13005-2-ludovic.barre@st.comSigned-off-by:
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Lubomir Rintel authored
The $nodename allows only "mmc@*" whereas the example node is named "sdhci". Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200317093922.20785-19-lkundrak@v3.skSigned-off-by:
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Ulf Hansson authored
The error path for sanitize operations that completes with -ETIMEDOUT, is tightly coupled with the internal request handling code of the core. More precisely, mmc_wait_for_req_done() checks for specific sanitize errors. This is not only inefficient as it affects all types of requests, but also hackish. Therefore, let's improve the behaviour by moving the error path out of the mmc core. To do that, retuning needs to be held while running the sanitize operation. Moreover, to avoid exporting unnecessary symbols to the mmc block module, let's move the code into the mmc_ops.c file. While updating the actual code, let's also take the opportunity to clean up some of the mess around it. Signed-off-by:
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- 24 Mar, 2020 36 commits
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Masahiro Yamada authored
Use the FIELD_GET macro to get access to the register fields. Delete the shift macros. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Link: https://lore.kernel.org/r/20200312110050.21732-1-yamada.masahiro@socionext.comSigned-off-by:
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Cristian Birsan authored
The sdhci_at91_set_clks_presets() function is called multiple times at runtime and the messages are shown on the console. Display clk mul, gck rate and clk base for debug purpose only. Signed-off-by:
Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200312142904.232822-1-tudor.ambarus@microchip.comSigned-off-by:
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Nicolas Saenz Julienne authored
The controller needs a valid bus voltage in its power register regardless of whether an external regulator is taking care of the power supply. The sdhci core already provides a helper function for this, sdhci_set_power_and_bus_voltage(), so create a bcm2711 specific 'struct sdhci_ops' which makes use of it. Signed-off-by:
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by:
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Nicolas Saenz Julienne authored
The sdhci core provides a helper function with the same functionality as this controller's set_power() callback. Use it instead. Signed-off-by:
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Nicolas Saenz Julienne authored
The sdhci core provides a helper function with the same functionality as this controller's set_power() callback. Use it instead. Signed-off-by:
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Nicolas Saenz Julienne authored
The sdhci core provides a helper function with the same functionality as this controller's set_power() callback. Use it instead. Signed-off-by:
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Nicolas Saenz Julienne authored
The sdhci core provides a helper function with the same functionality as this controller's set_power() callback. Use it instead. Signed-off-by:
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Nicolas Saenz Julienne authored
Some controllers diverge from the standard way of setting power and need their bus voltage register to be configured regardless of the whether they use regulators. As this is a common pattern across sdhci hosts, create a helper function. Signed-off-by:
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Takashi Iwai authored
Since snprintf() returns the would-be-output size instead of the actual output size, the succeeding calls may go beyond the given buffer limit. Fix it by replacing with scnprintf(). Signed-off-by:
Takashi Iwai <tiwai@suse.de> Link: https://lore.kernel.org/r/20200311080439.13928-1-tiwai@suse.deSigned-off-by:
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Johan Jonker authored
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "synopsys-dw-mshc-common.yaml#" allOf: - $ref: "mmc-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine synopsys-dw-mshc.yaml, synopsys-dw-mshc-common.yaml and mmc-controller.yaml it gives this error: Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.example.dt.yaml: mmc@12200000: 'clock-freq-min-max' does not match any of the regexes: '^.*@[0-9]+$', '^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)| uhs-(sdr(12|25|50|104)|ddr50))$', 'pinctrl-[0-9]+' 'clock-freq-min-max' is deprecated, so replace it by 'max-frequency'. make ARCH=arm dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200307160556.16226-1-jbx6244@gmail.comSigned-off-by:
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Sowjanya Komatineni authored
Tegra sdhci host supports HW busy detection of the device busy signaling over data0 lane. So, this patch enables host capability MMC_CAP_wAIT_WHILE_BUSY. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1583941675-9884-2-git-send-email-skomatineni@nvidia.com [Ulf: Lumped together the caps assignments] Signed-off-by:
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Sowjanya Komatineni authored
Tegra host supports HW busy detection and timeouts based on the count programmed in SDHCI_TIMEOUT_CONTROL register and max busy timeout it supports is 11s in finite busy wait mode. Some operations like SLEEP_AWAKE, ERASE and flush cache through SWITCH commands take longer than 11s and Tegra host supports infinite HW busy wait mode where HW waits forever till the card is busy without HW timeout. This patch implements Tegra specific set_timeout sdhci_ops to allow switching between finite and infinite HW busy detection wait modes based on the device command expected operation time. Signed-off-by:
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Faiz Abbas authored
Add power management ops which save and restore the driver context and facilitate a system suspend and resume. Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200305151228.24692-1-faiz_abbas@ti.comSigned-off-by:
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Wolfram Sang authored
After refactoring, 'ret' variable is superfluous. Remove it. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200213163715.8212-1-wsa+renesas@sang-engineering.comSigned-off-by:
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Geert Uytterhoeven authored
Use the existing BITS_PER_LONG helper definition instead of calculating this value. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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Veerabhadrarao Badiganti authored
Update cqhci memory ioresource name from cqhci_mem to cqhci since suffix _mem is redundant. Only sdhci-msm driver is making use of this resource as of now. No other vendor's driver is using it. So this update shouldn't affect any other vendor's cqhci functionality. Signed-off-by:
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by:
Douglas Anderson <dianders@chromium.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1583328320-9981-1-git-send-email-vbadigan@codeaurora.orgSigned-off-by:
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Veerabhadrarao Badiganti authored
When SDHC gets reset (E.g. in runtime suspend path), CQE also gets reset and goes to disable state. But s/w state still points it as CQE is in enabled state. Since s/w and h/w states goes out of sync, it results in s/w request timeout for subsequent CQE requests. To synchronize CQE s/w and h/w state during SDHC reset, explicitly deactivate CQE just before SDHC reset. Signed-off-by:
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Adrian Hunter authored
Host controllers can reset CQHCI either directly or as a consequence of host controller reset. Add cqhci_deactivate() which puts the CQHCI driver into a state that is consistent with that. Signed-off-by:
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Gustavo A. R. Silva authored
The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732 ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by:
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Veerabhadrarao Badiganti authored
Supply a separate sg list for each of the request in non-blocking IO test cases where two requests will be issued at same time. Otherwise, sg memory may get unmapped when a request is done while same memory is being accessed by controller from the other request, and it leads to iommu errors with below call stack: __arm_lpae_unmap+0x2e0/0x478 arm_lpae_unmap+0x54/0x70 arm_smmu_unmap+0x64/0xa4 __iommu_unmap+0xb8/0x1f0 iommu_unmap_fast+0x38/0x48 __iommu_dma_unmap+0x88/0x108 iommu_dma_unmap_sg+0x90/0xa4 sdhci_post_req+0x5c/0x78 mmc_test_start_areq+0x10c/0x120 [mmc_test] mmc_test_area_io_seq+0x150/0x264 [mmc_test] mmc_test_rw_multiple+0x174/0x1c0 [mmc_test] mmc_test_rw_multiple_sg_len+0x44/0x6c [mmc_test] mmc_test_profile_sglen_wr_nonblock_perf+0x6c/0x94 [mmc_test] mtf_test_write+0x238/0x3cc [mmc_test] Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Tested-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Acked-by:
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Veerabhadrarao Badiganti authored
CQE feature has been enabled on sdhci-msm. Add CQE reg map and reg names that need to be supplied for supporting CQE feature. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1582545470-11530-1-git-send-email-vbadigan@codeaurora.orgSigned-off-by:
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Baolin Wang authored
The Spreadtrum host controller supports HW busy detection for commands with R1B responses, but also for I/O operations. This means when the host gets a transfer complete event, that always indicates the busy signal is released. Let's inform the mmc core about this, via setting the corresponding MMC_CAP_WAIT_WHILE_BUSY flag, as to remove some redundant software busy polling. Signed-off-by:
Baolin Wang <baolin.wang7@gmail.com> Acked-by:
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Jérôme Pouiller authored
sdio_single_irq_set() was indented with a mix of tabs and spaces. Signed-off-by:
Jérôme Pouiller <jerome.pouiller@silabs.com> Link: https://lore.kernel.org/r/20200221163147.608677-1-Jerome.Pouiller@silabs.comSigned-off-by:
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Haibo Chen authored
In some low power mode, SoC will lose the pin state, so need to restore the pin state when resume back. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Link: https://lore.kernel.org/r/1582100757-20683-8-git-send-email-haibo.chen@nxp.comSigned-off-by:
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Haibo Chen authored
Currently, when use standard tuning, driver default disable DMA just before send tuning command. But on i.MX8 usdhc, this is not enough. Need also clear DMA_SEL. If not, once the DMA_SEL select AMDA2 before, even dma already disabled, when send tuning command, usdhc will still prefetch the ADMA script from wrong DMA address, then we will see IOMMU report some error which show lack of TLB mapping. Signed-off-by:
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Haibo Chen authored
On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the the 1st linux configure power/clock for the 2nd Linux. When the 2nd Linux is booting into rootfs stage, we let the 1st Linux to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump as following, after we clear the pending interrupt and halt CQCTL, issue gone. [ 1.334594] mmc2: Got command interrupt 0x00000001 even though no command operation was in progress. [ 1.334595] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 1.334599] mmc2: sdhci: Sys addr: 0xa05dcc00 | Version: 0x00000002 [ 1.345538] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000000 [ 1.345541] mmc2: sdhci: Argument: 0x00018000 | Trn mode: 0x00000033 [ 1.345543] mmc2: sdhci: Present: 0x01f88008 | Host ctl: 0x00000031 [ 1.345547] mmc2: sdhci: Power: 0x00000002 | Blk gap: 0x00000080 [ 1.357903] mmc2: sdhci: Wake-up: 0x00000008 | Clock: 0x0000003f [ 1.357905] mmc2: sdhci: Timeout: 0x0000008f | Int stat: 0x00000000 [ 1.357908] mmc2: sdhci: Int enab: 0x107f100b | Sig enab: 0x107f100b [ 1.357911] mmc2: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000502 [ 1.370268] mmc2: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b400 [ 1.370270] mmc2: sdhci: Cmd: 0x00000d1a | Max curr: 0x00ffffff [ 1.370273] mmc2: sdhci: Resp[0]: 0x00000b00 | Resp[1]: 0xffffffff [ 1.370276] mmc2: sdhci: Resp[2]: 0x328f5903 | Resp[3]: 0x00d00f00 [ 1.382132] mmc2: sdhci: Host ctl2: 0x00000000 [ 1.382135] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0xa2040208 [ 2.060932] mmc2: Unexpected interrupt 0x00004000. [ 2.065538] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 2.071720] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00000002 [ 2.077902] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001 [ 2.084083] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 2.090264] mmc2: sdhci: Present: 0x01f88009 | Host ctl: 0x00000011 [ 2.096446] mmc2: sdhci: Power: 0x00000002 | Blk gap: 0x00000080 [ 2.102627] mmc2: sdhci: Wake-up: 0x00000008 | Clock: 0x000010ff [ 2.108809] mmc2: sdhci: Timeout: 0x0000008f | Int stat: 0x00004000 [ 2.114990] mmc2: sdhci: Int enab: 0x007f1003 | Sig enab: 0x007f1003 [ 2.121171] mmc2: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000502 [ 2.127353] mmc2: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b400 [ 2.133534] mmc2: sdhci: Cmd: 0x0000371a | Max curr: 0x00ffffff [ 2.139715] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff [ 2.145896] mmc2: sdhci: Resp[2]: 0x328f5903 | Resp[3]: 0x00d00f00 [ 2.152077] mmc2: sdhci: Host ctl2: 0x00000000 [ 2.156342] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000 Signed-off-by:
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Haibo Chen authored
Add new esdhc_soc_data, with compatible string "fsl,imx8mm-usdhc". Signed-off-by:
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Haibo Chen authored
Since L4.15, community involve the commit 105819c8 ("mmc: core: use mrq->sbc when sending CMD23 for RPMB"), let the usdhc to decide whether to use ACMD23 for RPMB. This CMD23 for RPMB need to set the bit 31 to its argument, if not, the RPMB write operation will return general fail. According to the sdhci logic, SDMA mode will disable the ACMD23, and only in ADMA mode, it will chose to use ACMD23 if the host support. But according to debug, and confirm with IC, the imx6qpdl/imx6sx/imx6sl/imx7d do not support the ACMD23 feature completely. These SoCs only use the 16 bit block count of the register 0x4 (BLOCK_ATT) as the CMD23's argument in ACMD23 mode, which means it will ignore the upper 16 bit of the CMD23's argument. This will block the reliable write operation in RPMB, because RPMB reliable write need to set the bit31 of the CMD23's argument. This is the hardware limitation. So for imx6qpdl/imx6sx/imx6sl/imx7d, it need to broke the ACMD23 for eMMC, SD card do not has this limitation, because SD card do not support reliable write. For imx6ul/imx6ull/imx6sll/imx7ulp/imx8, it support the ACMD23 completely, it change to use the 0x0 register (DS_ADDR) to put the CMD23's argument in ADMA mode. This patch add a new flag ESDHC_FLAG_BROKEN_AUTO_CMD23, and add this flag to imx6q/imx6sx/imx6sl/imx7d, and due to the imx6sll share the same compatible string with imx6sx before, and imx6sll do not has this limitation, so add a new compatible string for imx6sll. Signed-off-by:
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Haibo Chen authored
After set the STROBE SLV delay target value, it need to wait some time to let the usdhc lock the REF and SLV clock. In normal case, 1~2us is enough for imx8/imx6 and imx7d, and 4~5us is enough for imx7ulp, but when do reboot stress test or do the bind/unbind stress test, sometimes need to wait about 10us to get the status lock. This patch optimize delay handle method, only print the warning message if the status is still not lock after 1ms delay. Signed-off-by:
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Haibo Chen authored
When force clock off, check the SDOFF of register PRSSTAT to make sure the clock is gate off. Before force clock on, check the SDSTB of register PRSSTAT to make sure the clock is stable, this will eliminate the clock glitch. Signed-off-by:
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Haibo Chen authored
strobe-dll-delay-target is the delay cell add on the strobe line. Strobe line the the uSDHC loopback read clock which is use in HS400 mode. Different strobe-dll-delay-target may need to set for different board/SoC. If this delay cell is not set to an appropriate value, we may see some read operation meet CRC error after HS400 mode select which already pass the tuning. This patch add the strobe-dll-delay-target setting in driver, so that user can easily config this delay cell in dts file. Signed-off-by:
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Haibo Chen authored
Add fsl,strobe-dll-delay-target binding. Signed-off-by:
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Haibo Chen authored
When pm_runtime_suspend is run, a call to SCFW power off the SS (SS is a power domain, usdhc belong to this SS power domain) in which the resource resides is made. The SCFW can power off the SS if no other resource in active in that SS. If so, all state associated with all the resources within the SS that is powered off is lost, this includes the clock rates, clock state etc. When pm_runtime_resume is called, the SS associated with that resource is powered up. But the clocks are left in the default state. This patch restore clock rate in pm_runtime_resume, make sure the clock is right rather than depending on the default state setting by SCFW. Signed-off-by:
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Haibo Chen authored
For Mega/Mix enabled SoCs like MX7D and MX6SX, uSDHC will lost power in LP mode no matter whether the MMC_KEEP_POWER flag is set or not. This may cause state misalign between kernel and HW, especially for SDIO3.0 WiFi cards. e.g. SDIO WiFi driver usually will keep power during system suspend. And after resume, no card re-enumeration called. But the tuning state is lost due to Mega/Mix. Then CRC error may happen during next data transfer. So we should always fire a mmc_retune_needed() for such type SoC to tell MMC core retuning is needed for next data transfer. mmc: sdhci-esdhci-imx: retune needed for Mega/Mix enabled SoCs Signed-off-by:
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Haibo Chen authored
When using jailhouse to support two Linux on i.MX8MQ EVK, we use the 1st Linux to configure pinctrl for the 2nd Linux. Then the 2nd Linux could use the mmc without pinctrl driver. So give a warning message when no pinctrl available, but no fail probe. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1582100563-20555-3-git-send-email-haibo.chen@nxp.comSigned-off-by:
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Haibo Chen authored
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE, we also do not need to handle controller native card detect interrupt for gpio cd type. If we wrong enabled the card detect interrupt for gpio case, it will cause a lot of unexpected card detect interrupts during data transfer which should not happen. Signed-off-by:
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