- 01 Jul, 2020 40 commits
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Aditya Pakki authored
On calling pm_runtime_get_sync() the reference count of the device is incremented. In case of failure, decrement the reference count before returning the error. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Aditya Pakki <pakki001@umn.edu> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Navid Emamdoost authored
The call to pm_runtime_get_sync increments the counter even in case of failure, leading to incorrect ref count. In case of failure, decrement the ref count before returning. Signed-off-by:
Navid Emamdoost <navid.emamdoost@gmail.com> Signed-off-by:
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Navid Emamdoost authored
in amdgpu_display_crtc_set_config, the call to pm_runtime_get_sync increments the counter even in case of failure, leading to incorrect ref count. In case of failure, decrement the ref count before returning. Signed-off-by:
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Navid Emamdoost authored
in amdgpu_drm_ioctl the call to pm_runtime_get_sync increments the counter even in case of failure, leading to incorrect ref count. In case of failure, decrement the ref count before returning. Signed-off-by:
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Navid Emamdoost authored
in amdgpu_driver_open_kms the call to pm_runtime_get_sync increments the counter even in case of failure, leading to incorrect ref count. In case of failure, decrement the ref count before returning. Signed-off-by:
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Aditya Pakki authored
On calling pm_runtime_get_sync() the reference count of the device is incremented. In case of failure, decrement the reference count before returning the error. Signed-off-by:
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Lei Guo authored
[WHY] The memcpy() function copies n bytes from memory area src to memory area dest. So specify the firmware size in bytes. [How] Correct the calculation. Acked-by:
Lei Guo <raykwok1150@163.com> Reviewed-by:
Junwei Zhang <zjunweihit@163.com> Signed-off-by:
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Alex Deucher authored
Add rename the gpu busy percentage for consistency and add the mem busy percentage documentation. Reviewed-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Alex Deucher authored
Vega10 and previous asics use one interface, vega20 and newer use another. Reviewed-by:
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Qiushi Wu authored
kobject_init_and_add() takes reference even when it fails. If this function returns an error, kobject_put() must be called to properly clean up the memory associated with the object. Signed-off-by:
Qiushi Wu <wu000273@umn.edu> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Felix Kuehling authored
Use WARN to print messages with backtrace when evictions are triggered. This can help determine the root cause of evictions and help spot driver bugs triggering evictions unintentionally, or help with performance tuning by avoiding conditions that cause evictions in a specific workload. The messages are controlled by a new module parameter that can be changed at runtime: echo Y > /sys/module/amdgpu/parameters/debug_evictions echo N > /sys/module/amdgpu/parameters/debug_evictions Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Tom St Denis authored
Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Alvin Lee authored
Get the values from VBIOS table Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Bernard Zhao authored
In function fill_iram_v_2, the ram_table->bright_neg_gain`s first element [0][0] seems to be missing. This change is just to make the code a bit readable. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Joseph Greathouse authored
SDMA ULV can benefit low-power modes, but can sometimes cause latency increases in small SDMA transfers. Server SKUs have a different trade-off space in this domain, so this configures the server SKUs' ULV hysteresis times differently than consumer SKUs'. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lorenz Brun authored
The existing code used the major version number of the DRM driver instead of the device major number of the DRM subsystem for validating access for a devices cgroup. This meant that accesses allowed by the devices cgroup weren't permitted and certain accesses denied by the devices cgroup were permitted (if they matched the wrong major device number). Signed-off-by:
Lorenz Brun <lorenz@brun.one> Fixes: 6b855f7b ("drm/amdkfd: Check against device cgroup") Reviewed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Anthony Koo authored
[Header Changes] - Add new initialization bits for driver to check firmware status - Add command for HW locking via DMUB Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] dmub FW running abnormal after resume from S0i3 due to data aliagnment issue. [How] Before having a solution for this issue, temparory not doing data pack. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] during S0i3, set power state is toggled a few times, and dmub uC will restart with current reset/hw_init. [How] Remove reset in set power state, and before doing hw_init, check if dmub is enabled, and doing FW autoload check only if dmub is already enabled. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dale Zhao authored
[Why] For some special timing with border, like DMT 640*480 72Hz, pipe split can't handle well. Thus, it will be black screen for these special timing. [How] Disable pipe split for these timing with borders as W/A. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] Multi-adapter calculate regamma table at the same time. Two thread used the same global variable cause race condition. [How] Change global buffer to local buffer Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] DC is very fast at link training and stream enablement which causes issues such as blackscreens for non-compliant monitors. [How] After debugging with scaler vendors we implement the minimum delays at the necessary locations to ensure the monitor does not hang. Delays are generic due to lack of IEEE OUI information on the failing displays. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why & How] DMUB command table should be allowed to be used only if dmcu is explicitly disabled. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Dmytro Laktyushkin authored
To allow code reuse with minimal duplication watermark calculation needs to be function pointer. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Rodrigo Siqueira authored
During the debugging process related to a hot-plug problem with 4k display, we realized that we had some issues related to the global state validation. This problem was not explicitly highlighted in the dmesg log, for this reason, this commit adds a function that converts `enum dc_status` to a human-readable string and appends the proper warning message in case of failure. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Jun Lei authored
[why] Dummy pstate latency actually varies between different UCLK frequencies, when calculating watermark C, if DAL always assumes worst case, then it can lead to dummy pstate not supported scenarios. [how] Rather than statically calculating dummy pstate using worst case, we store the entire table of UCLK to dummy pstate relationships. On a per mode basis, we calculate the actual UCLK lower limit, and use the dynamic worst case dummy pstate latency. This prevents the situation where we don't support full p-state (which will force high DPM), but still use low DPM dummy pstate latency. Signed-off-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Wenjing Liu authored
[why] The change causes some regression in a common use case. Will need more investigation before fixing the original issue. [how] This reverts commit fb8cf277. Signed-off-by:
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Dmytro Laktyushkin authored
We were updating mpcc if there were tree changes which is unnecessary since any mpcc being added or removed will automatically update the tree. Signed-off-by:
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Yongqiang Sun authored
[Why & How] Add emul specific hw function to dmub, in case of emulator is created, we can runtime switch between dmub emulator or dmub uC via is_virtual flag in dmub. Signed-off-by:
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po-tchen authored
[Why] The SDP deadline indicate the vertical time to send CRC infopacket in PSR. Signed-off-by:
po-tchen <po-ting.chen@amd.com> Reviewed-by:
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Martin Tsai authored
[Why] Some sprcified monitor scalar cannot recognize timing change on demand. Once the link phy disable and enable during a short period then the Sink protection mechanism could keep the screen in blank and cannot be recoverred. [How] To add 100ms delay between enable link phy and link training. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Anthony Koo authored
[Header Changes] - Add SDP transmission deadline for PSR config cmd Signed-off-by: -
Charlene Liu authored
[why] for audio on real TV issue. [how] -add wall clock programming for DPREF based when Pixel clock is done by DP DTO. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DML failures occur for 420 modes with dynamic pipe splitting enabled because the ChromaViewport exceeds the ChromaSurfaceWidth. This is caused by adding the viewport_width instead of the viewport_width_c. This similarly occurs for rotated modes due to the use of viewport_height instead of viewport_height_c. [How] Correct the calculations. Signed-off-by:
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Hugo Hu authored
This reverts commmit fd0293dd. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Roman Li authored
[Why] SOC_BOUNDING_BOX_VALID is unused and not required for dcn21. [How] Remove it. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] DSC calculations fail because the u16 bits_per_pixel from the DRM struct is being casted to the u8 drm_bpp parameters and locals. Integer wraparound is happening because this value is greater than 255. [How] Use u16 to match what's in the structure instead of u8. Signed-off-by:
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Wesley Chalmers authored
[WHY] Disabling DPG should happen after setting watermarks and clocks Signed-off-by:
Wesley Chalmers <wchalmer@amd.com> Reviewed-by:
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