- 18 Jan, 2024 13 commits
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: space required after that ',' (ctx:VxV) Signed-off-by:chenxuebing <chenxb_99091@126.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: space prohibited before that ',' (ctx:WxE) Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following enum go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following enum go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxV) Signed-off-by:
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: space required after that ',' (ctx:VxV) Signed-off-by:
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by:
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- 15 Jan, 2024 27 commits
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: need consistent spacing around '-' (ctx:WxV) Signed-off-by:
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: space required before the open parenthesis '(' ERROR: that open brace { should be on the previous line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: do not initialise globals to 0 Signed-off-by:
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: -
Ma Jun authored
If the RLC firmware is invalid because of wrong header size, the pointer to the rlc firmware is released in function amdgpu_ucode_request. There will be a null pointer error in subsequent use. So skip validation to fix it. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
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Hawking Zhang authored
Move ras capablity check to amdgpu_ras_check_supported. Driver will query ras capablity through psp interace, or vbios interface, or specific ip callbacks. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Hawking Zhang authored
Instead of traditional atomfirmware interfaces for RAS capability, host driver can query ras capability from psp starting from psp v13_0_6. v2: drop redundant local variable from get_ras_capability. Signed-off-by:
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Martin Leung authored
- Align the returned error code with legacy DP - Allow Z8 for multiplane configurations on DCN35 - Set default Z8 minimum residency for DCN35 - Rework DC Z10 restore - Enable Panel Replay for static screen use case - Add DP audio BW validation - Fix dml2 assigned pipe search - Ensure populate uclk in bb construction - Update P010 scaling cap - Reenable windowed mpo odm support - Fix DML2 watermark calculation - Clear OPTC mem select on disable - Floor to mhz when requesting dpp disp clock changes to SMU - Port DENTIST hang and TDR fixes to OTG disable W/A - Add logging resource checks - Add Replay IPS register for DMUB command table - Init link enc resources in dc_state only if res_pool presents - Allow IPS2 during Replay Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Martin Leung <martin.leung@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] For usb4 connector, AUX transaction is handled by dmub utilizing a differnt code path comparing to legacy DP connector. If the usb4 DP connector is disconnected, AUX access will report EBUSY and cause igt@kms_dp_aux_dev fail. [How] Align the error code with the one reported by legacy DP as EIO. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Power improvement over DCN314, but also addresses a functional issue where plane_state remains uncleared on pipes that aren't actually active. [How] Update the check to allow for zero streams to be treated as z8 allow. Update the check to remove plane count on the active stream case. Z8 will still be blocked based on stutter duration, which is likely to be the case for most multi plane configurations. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Match DCN314's policy. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The call currently does two things: 1. Exits DMCUB from idle optimization if it was in 2. Checks DMCUB scratch register to determine if we need to call DMCUB to do deferred HW restore and then sends the command if it's ready for it. By doing (1) we prevent driver idle from being renotified in the cases where driver had previously allowed DC level idle optimizations via dc_allow_idle_optimizations since it thinks: allow == dc->idle_optimizations_allowed ...and that the operation is a no-op. We want driver idle to be resent at the next opprotunity to do so for video playback cases. [How] Migrate all usecases of dc_z10_restore to only perform (2). Add extra calls to dc_allow_idle_optimizations to handle (1) and also keep SW state matching with when we requested enter/exit of DMCUB idle optimizations. Ensure cursor idle optimizations false always get called when IPS is supported. Further rework/redesign is needed to decide whether we need a separate level of DM allow vs DC allow and when to attempt re-entry. Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Reviewed-by:
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Tom Chung authored
[Why] Enable the Panel Replay if eDP panel and ASIC support. (prioritize Panel Replay over PSR) [How] - Setup the Panel Replay config during the device init (prioritize Panel Replay over PSR). - Separate the Replay init function into two functions amdgpu_dm_link_setup_replay() and amdgpu_dm_set_replay_caps() to fix the issue in the earlier commit that cause PSR and Replay enabled at the same time. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Tested-by:
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George Shen authored
[Why] Timings with small HBlank (such as CVT RBv2) can result in insufficient HBlank bandwidth for audio SDP transmission when DSC is active. This will cause some higher bandwidth audio modes to fail. The combination of CVT RBv2 timings + DSC can commonly be encountered in MST scenarios. [How] Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST cases and filter out modes that cannot be supported with the current timing config. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[Why & How] DML2 currently finds assigned pipes in array order rather than the existing linked list order. This results in rearranging pipe order on flip and more importantly otg inst and pipe idx mismatch. This change preserves the order of existing pipes and guarantees the head pipe will have matching otg inst and pipe idx. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by:
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Alvin Lee authored
[Description] - For some SKUs, the optimal DCFCLK for each UCLK is less than the smallest DCFCLK STA target due to low memory bandwidth. There is an assumption that the DCFCLK STA targets will always be less than one of the optimal DCFCLK values, but this is not true for SKUs that have low memory bandwidth. In this case we need to populate the optimal UCLK for each DCFCLK STA targets as the max UCLK freq. - Also fix a bug in DML where start_state is not assigned and used correctly. Reviewed-by:
Samson Tam <samson.tam@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Charlene Liu authored
[Why] Keep the same as previous APU and also insert clock dump Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by:
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Ovidiu Bunea authored
[Why] core_mode_programming in DML2 should output watermark calculations to locals, but it incorrectly uses mode_lib [How] update code to match HW DML2 Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Ilya Bakoulin authored
[Why] Not clearing the memory select bits prior to OPTC disable can cause DSC corruption issues when attempting to reuse a memory instance for another OPTC that enables ODM. [How] Clear the memory select bits prior to disabling an OPTC. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Wenjing Liu authored
[Why] SMU uses discrete dpp and disp clock levels. When we submit SMU request for clock changes in Mhz we need to floor the requested value from Khz so SMU will choose the next higher clock level in Khz to set. If we ceil to Mhz, SMU will have to choose the next higher clock level after the ceil, which could result in unnecessarily jumpping to the next level. For example, we request 1911,111Khz which is exactly one of the SMU preset level. If we pass 1912Mhz, SMU will choose 2150,000 khz. If we pass 1911Mhz, SMU will choose 1911,111kHz, which is the expected value. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We can experience DENTIST hangs during optimize_bandwidth or TDRs if FIFO is toggled and hangs. [How] Port the DCN35 fixes to DCN314. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Charlene Liu authored
[Why] When mapping resources, resources could be unavailable. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: space prohibited before that '++' (ctx:WxB) Signed-off-by:
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chenxuebing authored
Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: trailing statements should be on next line Signed-off-by: -
chenxuebing authored
Fix the following errors reported by checkpatch: spaces required around that '=' (ctx:VxV) Signed-off-by:
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