- 31 Oct, 2023 15 commits
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Ben Skeggs authored
- disable I2C completely when GSP-RM detected Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-14-skeggsb@gmail.com
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Ben Skeggs authored
- disable GPIO completely when GSP-RM detected Signed-off-by:
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Ben Skeggs authored
- disable FUSE completely when GSP-RM detected Signed-off-by:
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Ben Skeggs authored
- add (initial) R535 implementation of FB, need VRAM size etc for boot - expose a way to "wrap" vram at a specific address/size as a standard nvkm_memory allocation, which will be used to write PTEs etc for RM- defined memory regions Signed-off-by:
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Ben Skeggs authored
- disable FAULT completely when GSP-RM detected - SVM support will be disabled when running on RM because of this Signed-off-by:
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Ben Skeggs authored
- add R535 implementation of DEVINIT, we need some of this for boot - add display disable fuse for ga100- Signed-off-by:
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Ben Skeggs authored
- disable BUS completely when GSP-RM detected Signed-off-by:
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Ben Skeggs authored
- (temporarily) disable if GSP-RM detected, will be added later - move BAR2 teardown from dtor(), it doesn't belong there Signed-off-by:
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Ben Skeggs authored
- disable ACR completely when GSP-RM detected Signed-off-by:
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Ben Skeggs authored
- move TOP after GSP, so we can disable TOP if GSP is in use - provide plumbing to support falcon-only and GSP-RM paths - provide a method for subdevs to detect GSP-RM paths - split tu102/tu116/ga100 paths from gv100, which can't support GSP-RM Signed-off-by:
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Ben Skeggs authored
RM (and GH100) support 8 NVJPG instances. Signed-off-by:
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Ben Skeggs authored
RM (and GH100) support 8 NVDEC instances. Signed-off-by:
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Ben Skeggs authored
This was cargo-culted from traces of RM when the code was written, but we probably shouldn't be touching NV_PFB regs while GSP-RM is running. From traces, it looks like NVIDIA dropped this sometime between 510.54 and 515.48.07, so I guess we can too. Signed-off-by:
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.7-2023-10-27: amdgpu: - RAS fixes - Seamless boot fixes - NBIO 7.7 fix - SMU 14.0 fixes - GC 11.5 fixes - DML2 fixes - ASPM fixes - VPE fixes - Misc code cleanups - SRIOV fixes - Add some missing copyright notices - DCN 3.5 fixes - FAMS fixes - Backlight fix - S/G display fix - fdinfo cleanups - EXT_COHERENT fixes for APU and NUMA systems amdkfd: - Misc fixes - Misc code cleanups - SVM fixes Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v6.7-rc1: drm-misc-next-2023-10-19 + following: UAPI Changes: Cross-subsystem Changes: - Convert fbdev drivers to use fbdev i/o mem helpers. Core Changes: - Use cross-references for macros in docs. - Make drm_client_buffer_addb use addfb2. - Add NV20 and NV30 YUV formats. - Documentation updates for create_dumb ioctl. - CI fixes. - Allow variable number of run-queues in scheduler. Driver Changes: - Rename drm/ast constants. - Make ili9882t its own driver. - Assorted fixes in ivpu, vc4, bridge/synopsis, amdgpu. - Add planar formats to rockchip. Signed-off-by:
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- 27 Oct, 2023 8 commits
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Umio Yasuno authored
Remove unused variables from amdgpu_show_fdinfo Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Umio Yasuno <coelacanth_dream@protonmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rob Clark authored
Some of the fields that are handled by drm_show_fdinfo() crept back in when rebasing the patch. Remove them again. Fixes: 376c25f8 ("drm/amdgpu: Switch to fdinfo helper") Reviewed-by:
Rob Clark <robdclark@chromium.org> Reviewed-by: <alexander.deucher@amd.com> Co-developed-by:
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Kenneth Feng authored
avoid to disable gfxhub interrupt when driver is unloaded on gmc 11 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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David Francis authored
On gfx943 APU, EXT_COHERENT should give MTYPE_CC for local and MTYPE_UC for nonlocal memory. On NUMA systems, local memory gets the local mtype, set by an override callback. If EXT_COHERENT is set, memory will be set as MTYPE_UC by default, with local memory MTYPE_CC. Add an option in the override function for this case, and add a check to ensure it is not used on UNCACHED memory. V2: Combined APU and NUMA code into one patch V3: Fixed a potential nullptr in amdgpu_vm_bo_update Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Candice Li authored
Retrieve correctable error count from ce_count_lo_chip instead of mca_umc_status. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Candice Li authored
Use ErrorCodeExt field to identify data parity error in replay mode. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Mukul Joshi authored
Fix a typo in parsing of the GC info table header when reading the IP discovery table. Fixes: 0e64c9aa ("drm/amdgpu: add type conversion for gc info") Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Hamza Mahfooz authored
An assignment statement was reversed during a refactor which effectively disabled S/G display outright. Since, we use adev->mode_info.gpu_vm_support to indicate to the rest of the driver that S/G display should be enabled and currently it is always set to false. So, to fix this set adev->mode_info.gpu_vm_support's value to that of init_data.flags.gpu_vm_support (and not vice versa). Fixes: 098c1307 ("drm/amd/display: enable S/G display for for recent APUs by default") Reported-by:
Mark Broadworth <mark.broadworth@amd.com> Tested-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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- 26 Oct, 2023 17 commits
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James Zhu authored
amdxcp unloads incompletely, and below error will be seen during load/unload, sysfs: cannot create duplicate filename '/devices/platform/amdgpu_xcp.0' devres_release_group will free xcp device at first, platform device will be unregistered later in platform_device_unregister. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
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Li Ma authored
Modify the print format of the fractional part to avoid display error. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
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Lijo Lazar authored
PCI domain/segment information of xccs is available through ACPI DSM methods. Consider that also while looking for devices. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Acked-by:
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Lin.Cao authored
In SR-IOV environment, the value of pcie_table->num_of_link_levels will be 0, and num_of_levels - 1 will cause array index out of bounds Signed-off-by:
Lin.Cao <lincao12@amd.com> Acked-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
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Lijo Lazar authored
Issue a read to confirm the register write before ringing doorbell. With multiple XCCs there is chance for race condition. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Yifan Zhang authored
is_mode1_reset_supported may be called before smu init, when smu_context is unitialized in driver load/unload test. Call smu_cmn_get_smc_version explicitly in is_mode1_reset_supported. v2: apply to aldebaran in case is_mode1_reset_supported will be uncommented (Candice Li) Fixes: 710d9cae ("drm/amd/pm: drop most smu_cmn_get_smc_version in smu") Signed-off-by:
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Tao Zhou authored
Add DF block and RAS poison mode query for DF v4_6_2. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Acked-by:
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Lijo Lazar authored
Use subrevision of IP version in discovery table to identify SOC revision id for NBIO v7.9 SOCs. Only newer bootloaders update subrevision field. Signed-off-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Aric Cyr authored
DC v3.2.256 Summary: * Fixes null-deref regression after "drm/amd/display: Update OPP counter from new interface" * Fixes display flashing when VSR and HDR enabled on dcn32 * Fixes dcn3x intermittent hangs due to FPO * Fixes MST Multi-Stream light up on dcn35 * Fixes green screen on DCN31x when DVI and HDMI monitors attached * Adds DML2 improvements * Adds idle power optimization improvements * Accommodates panels with lower nit backlight * Updates SDP VSC colorimetry from DP test automation request * Reverts "drm/amd/display: allow edp updates for virtual signal" Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] To enable automated testing through IGT, expose an API that is accessible through debugfs to query current status of SubVP feature. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Iswara Nagulendran authored
[HOW&WHY] Reading the value from DP_EDP_BACKLIGHT_MODE_SET_REGISTER, DPCD 0x721 before setting the BP_EDP_PANEL_LUMINANC_CONTROL_ENABLE bit to ensure there are no accidental overwrites. Reviewed-by:
Sreeja Golui <sreeja.golui@amd.com> Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Acked-by:
Iswara Nagulendran <iswara.nagulendran@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Currently causes some DP link layer failures, backing out until the failures are root caused. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] LUT params are not cleared after setting blend TF, which can lead to same params being used for the shaper, if the shaper func is bypassed. [How] Set lut_params to NULL after program_1dlut. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Samson Tam authored
[Why] In cases where number of pipes available is less than num_opp, there will opp instances that are null [How] Add null check to skip over these opp instances Fixes: 40de8403 ("drm/amd/display: Update OPP counter from new interface") Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Alvin Lee authored
Provide DCN32 specific sequence and update DCN30 sequence Reviewed-by:
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Samson Tam authored
[Why] Helper function calculates num_ways using 32-bit. But is returned as 8-bit. If num_ways exceeds 8-bit, then it reports back the incorrect num_ways and erroneously uses MALL when it should not [How] Make returned value 32-bit and convert after it checks against caps.cache_num_ways, which is under 8-bit Reviewed-by:
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Rodrigo Siqueira authored
This commit adds the amdgpu_dm_plane_ prefix for all functions in the amdgpu_dm_plane.c. This change enables an easy way to filter code paths via ftrace. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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