- 07 Mar, 2023 40 commits
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lyndonli authored
Actually, the drm_dev_enter in psp_cmd_submit_buf does not protect anything. If DRM device is unplugged, it will always check the condition in WARN_ON. So drop drm_dev_enter and drm_dev_exit in psp_cmd_submit_buf. When removing amdgpu, the calling order is as follows: amdgpu_pci_remove drm_dev_unplug amdgpu_driver_unload_kms amdgpu_device_fini_hw amdgpu_device_ip_fini_early psp_hw_fini psp_ras_terminate psp_ta_unloadye psp_cmd_submit_buf [ 4507.740388] Call Trace: [ 4507.740389] <TASK> [ 4507.740391] psp_ta_unload+0x44/0x70 [amdgpu] [ 4507.740485] psp_ras_terminate+0x4d/0x70 [amdgpu] [ 4507.740575] psp_hw_fini+0x28/0xa0 [amdgpu] [ 4507.740662] amdgpu_device_fini_hw+0x328/0x442 [amdgpu] [ 4507.740791] amdgpu_driver_unload_kms+0x51/0x60 [amdgpu] [ 4507.740875] amdgpu_pci_remove+0x5a/0x140 [amdgpu] [ 4507.740962] ? _raw_spin_unlock_irqrestore+0x27/0x43 [ 4507.740965] ? __pm_runtime_resume+0x60/0x90 [ 4507.740968] pci_device_remove+0x39/0xb0 [ 4507.740971] device_remove+0x46/0x70 [ 4507.740972] device_release_driver_internal+0xd1/0x160 [ 4507.740974] driver_detach+0x4a/0x90 [ 4507.740975] bus_remove_driver+0x6c/0xf0 [ 4507.740976] driver_unregister+0x31/0x50 [ 4507.740977] pci_unregister_driver+0x40/0x90 [ 4507.740978] amdgpu_exit+0x15/0x120 [amdgpu] v2: fix commit message style issue Signed-off-by:lyndonli <Lyndon.Li@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Felix Kuehling authored
Treat the last page in a non-contiguous range as part of the following contiguous range. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-and-tested-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Reviewed-by:
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Lijo Lazar authored
Initial version of PMFW interface and message headers for SMU 13.0.6 support. v2: squash in location fixes (Alex) v3: squash in updates (Alex) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Hawking Zhang authored
Add mp v13_0_6 register offset and shift masks header files v2: update headers (Alex) Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Orlando Chamberlain authored
Commit 3840c5bc ("drm/amdgpu: disentangle runtime pm and vga_switcheroo") made amdgpu only register a vga_switcheroo client for GPU's with PX, however AMD GPUs in dual gpu Apple Macbooks do need to register, but don't have PX. Instead of AMD's PX, they use apple-gmux. Use apple_gmux_detect() to identify these gpus, and pci_is_thunderbolt_attached() to ensure eGPUs connected to Dual GPU Macbooks don't register with vga_switcheroo. Fixes: 3840c5bc ("drm/amdgpu: disentangle runtime pm and vga_switcheroo") Link: https://lore.kernel.org/amd-gfx/20230210044826.9834-10-orlandoch.dev@gmail.com/Signed-off-by:
Orlando Chamberlain <orlandoch.dev@gmail.com> Signed-off-by:
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Aric Cyr authored
In this new version there are two major changes: 1) Transitioning to the new DC commit sequence There is an extended effort to migrate to the new DC commit sequence that better adheres to the DCN hardware constraints. Most of the code was upstreamed already but not connected to amdgpu_dm, and in this new DC version, our DM finally started to use it for all ASICs. This should improve stability and enable us to improve how pipe split works. 2) Drop old CONFIG_DRM_AMD_DC_DCN in favor of new CONFIG_DRM_AMD_DC_FP For historical reasons, we created CONFIG_DRM_AMD_DC_DCN to isolate FPU-related code to only be used for DCN. Over the years, we lost control over this guard, and it was spread in multiple areas. In this new DC version, there is an effort to remove all unnecessary CONFIG_DRM_AMD_DC_DCN and replace the others for CONFIG_DRM_AMD_DC_FP, which better describes which type of code this guard is intended for. Finally, this version brings along the following: - Enable HostVM based on rIOMMU active - Keep PHY active for dp confi - Improves Z8 - Update clock table - Code and directives clean up Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The function dc_update_planes_and_stream handles multiple cases where DC needs to remove and add planes in the commit tail phase. After Linux started to use this function, some of the IGT kms_plane started to fail; one good example to illustrate why the new sequence regressed IGT is the subtest plane-position-hole which has the following diagram as a template: +--------------------+ +-----------------------+ | +-----+ | | +-----+ | | | | | | | +-----+ | | | +--+ | ==> | | | | | | | |__| | | +-|---+ | | | | | +-----+ | | | | | +--------------------+ +-----------------------+ (a) Final image (b) Composed image IGT expects image (a) as the final result of two plane compositions as described in figure (b). After the migration to the new sequence, the last plane order is changed, and DC generates the following image: +---------------------+ | +-----+ | | | | | | | | | | +-----+ | | | +---------------------+ Notice that the generated image by DC is different because the small square that should be composed on top of the primary plane is below the primary plane. For this reason, the CRC will mismatch with the expected value. Since the function dc_add_all_planes_for_stream re-append all the new planes back to the dc_validation_set, this commit ensures that the original sequence is maintained. After this change, all CI tests in all ASICs start to pass again. Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Rodrigo Siqueira authored
[Why & How] This commit is part of a sequence of changes that replaces the commit sequence used in the DC with a new one. As a result of this transition, we moved some specific parts from the commit sequence and brought them to amdgpu_dm. This commit adds a wrapper inside DM that enable our drivers to do any necessary preparation or change before we offload the plane/stream update to DC. Reviewed-by:
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Rodrigo Siqueira authored
[Why & How] DC now uses a new commit sequence which is more robust since it addresses cases where we need to reorganize pipes based on planes and other parameters. As a result, this new commit sequence reset the DC state by cleaning plane states and re-creating them accordingly with the need. For this reason, the dce_transform_set_pixel_storage_depth can be invoked after a plane state is destroyed and before its re-creation. In this situation and on DCE devices, DC will hit a condition that will trigger a dmesg log that looks like this: Console: switching to colour frame buffer device 240x67 ------------[ cut here ]------------ [..] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 5603 07/28/2020 RIP: 0010:dce_transform_set_pixel_storage_depth+0x3f8/0x480 [amdgpu] [..] RSP: 0018:ffffc9000202b850 EFLAGS: 00010293 RAX: ffffffffa081d100 RBX: ffff888110790000 RCX: 000000000000000c RDX: ffff888100bedbf8 RSI: 0000000000001a50 RDI: ffff88810463c900 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000007 R10: 0000000000000001 R11: 0000000000000f00 R12: ffff88810f500010 R13: ffff888100bedbf8 R14: ffff88810f515688 R15: 0000000000000000 FS: 00007ff0159249c0(0000) GS:ffff88840e940000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ff01528e550 CR3: 0000000002a10000 CR4: 00000000003506e0 Call Trace: <TASK> ? dm_write_reg_func+0x21/0x80 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] dc_stream_set_dither_option+0xfb/0x130 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_crtc_configure_crc_source+0x10b/0x190 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_atomic_commit_tail+0x20a8/0x2a90 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] ? free_unref_page_commit+0x98/0x170 ? free_unref_page+0xcc/0x150 commit_tail+0x94/0x120 drm_atomic_helper_commit+0x10f/0x140 drm_atomic_commit+0x94/0xc0 ? drm_plane_get_damage_clips.cold+0x1c/0x1c drm_client_modeset_commit_atomic+0x203/0x250 drm_client_modeset_commit_locked+0x56/0x150 drm_client_modeset_commit+0x21/0x40 drm_fb_helper_lastclose+0x42/0x70 amdgpu_driver_lastclose_kms+0xa/0x10 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] drm_release+0xda/0x110 __fput+0x89/0x240 task_work_run+0x5c/0x90 do_exit+0x333/0xae0 do_group_exit+0x2d/0x90 __x64_sys_exit_group+0x14/0x20 do_syscall_64+0x5b/0x80 ? exit_to_user_mode_prepare+0x1e/0x140 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7ff016ceaca1 Code: Unable to access opcode bytes at RIP 0x7ff016ceac77. RSP: 002b:00007ffe7a2357e8 EFLAGS: 00000246 ORIG_RAX: 00000000000000e7 RAX: ffffffffffffffda RBX: 00007ff016e15a00 RCX: 00007ff016ceaca1 RDX: 000000000000003c RSI: 00000000000000e7 RDI: 0000000000000000 RBP: 0000000000000000 R08: ffffffffffffff78 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007ff016e15a00 R13: 0000000000000000 R14: 00007ff016e1aee8 R15: 00007ff016e1af00 </TASK> Since this issue only happens in a transition state on DC, this commit replace BREAK_TO_DEBUGGER with DC_LOG_DC. Reviewed-by:
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Rodrigo Siqueira authored
[Why & How] The old dc_commit_updates_for_stream lacks manipulation for many corner cases where the DC feature requires special attention; as a result, it starts to show its limitation (e.g., the SubVP feature is not supported by it, among other cases). To modernize and unify our internal API, this commit replaces the old dc_commit_updates_for_stream with dc_update_planes_and_stream, which has more features. Reviewed-by:
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Rodrigo Siqueira authored
[Why & How] There are two functions responsible for handling the DC commit state: dc_commit_state and dc_commit_streams. Both have the same goal, but dc_commit_streams surpess dc_commit_state in terms of completeness. For this reason, maintaining these two functions makes maintainability unnecessarily complicated. This commit replaces the old dc_commit_state in favor of dc_commit_streams, and removes the old dc_commit_state. Reviewed-by:
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Rodrigo Siqueira authored
[Why & How] In the commit 32953485 ("drm/amd/display: Do not update DRR while BW optimizations pending"), a modification was added to avoid adjusting DRR if optimized bandwidth is set. This change was only intended for DCN, but one part of the patch changed the code path for DCE devices and caused regressions to the kms_vrr test. To address this problem, this commit adds a modification in which dc_stream_adjust_vmin_vmax will be fully executed in DCE devices. Fixes: 32953485 ("drm/amd/display: Do not update DRR while BW optimizations pending") Reviewed-by:
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Alvin Lee authored
[Description] - For pipe harvesting cases, the pipe index does not necessarily match up with the OTG instance, so pass index by OTG Instance instead - For pipe split cases pass HUBP instance, since the split index is only used for HUBP programming - Also check for OPP ID when accessing opp for pipe harvesting cases Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Gabe Teeger authored
[Why] There is underflow and flickering occuring. The underflow stops when hostvm is forced to active. According to policy, hostvm should be enabled if riommu is active, but this is not taken into account when deciding whether to enable hostvm. [What] For DCN314, set hostvm to true if riommu is active. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Gabe Teeger <gabe.teeger@amd.com> Tested-by:
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Wayne Lin authored
[Why & How] drm_dp_remove_payload() interface was changed. Correct amdgpu dm code to pass the right parameter to the drm helper function. Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Alvin Lee authored
[Description] - For min FCLK, choose the min of 300Mhz and PMFW requirement - Also only apply min DET check in DML for non-UR cases Reviewed-by:
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Harry Wentland authored
[Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in the future. Reviewed-by:
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Harry Wentland authored
[Why & How] DC is littered with many DCN guards that are not needed. Drop them. Reviewed-by:
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Harry Wentland authored
[Why] DM is littered with DCN guards leading to frequent breakages on non-DCN builds when new code is added. [How] Remove all guards that are not needed. Reviewed-by:
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Agustin Gutierrez authored
[Why] Current hotplug sequence causes temporary hang at the re-entry of the optimized power state. [How] Keep a PHY active when detecting DP signal + DPMS active Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Tested-by:
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Chris Park authored
[Why] Runtime initialization of register addresses define duplicate register offsets in resource file, and makes register offsets in sub-block defined for compile time initialization obsolete. [How] Remove obsolete sub block register offsets that is no longer referenced. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Wenjing Liu authored
[why] Link components should not reply on dc_link_exports to access link function in other link components. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] link component should only have one interface serving dc. [how] We are moving dc_link functions exposed to DM to dc_link_exports and unify link component interface in link.h with function pointer to match the style of other dc component. This is the third step to move dc_link functions under protocols folder to dc_link_exports. Reviewed-by:
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Wenjing Liu authored
[Why & How] - We have added link_dp_dpia_bw code but it is not currently added in makefile. We are adding this to makefile so it would be built. - Remove unused dc_link.h Reviewed-by:
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Wenjing Liu authored
[why] link component should only have one interface serving dc. [how] We are moving dc_link functions exposed to DM to dc_link_exports and unify link component interface in link.h with function pointer to match the style of other dc component. This is the second step to move dc_link functions under link root folder to dc_link_exports. Reviewed-by:
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Wenjing Liu authored
[why] link component should only have one interface serving dc. [how] We are moving dc_link functions exposed to DM to dc_link_exports and unify link component interface in link.h with function pointer to match the style of other dc component. This is the first step to move dc_link functions under accessories folder to dc_link_exports. Reviewed-by:
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Harry Wentland authored
[Why & How] DSC needs DCN but we are trying reduce the usage of the DCN flag. It's easier to build the DSC code sprinkled around DC core and the DMs and just guard the place where DSC uses floating point code. Since DSC is never enabled on non-DCN ASICs this won't have any effect. Reviewed-by:
Hamza Mahfooz <Hamza.Mahfooz@amd.com> Acked-by:
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Harry Wentland authored
[Why & How] DM should never use a non-interface function to call into DC. The original code is incorrect on ASICs that don't use DCN20's remove_stream_from_ctx function. Reviewed-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by:
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Harry Wentland authored
[Why & How] There is no reason we still need a config option for this. Reviewed-by:
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Mike Hsieh authored
[WHY] There is a typo in dc_dsc_config_options structure [HOW] Fix the typo Reviewed-by:
Mike Hsieh <Mike.Hsieh@amd.com> Tested-by:
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Harry Wentland authored
[Why & How] This fixes a couple misplaced CONFIG_DRM_AMD_DC_DCN blocks. Reviewed-by:
Sun peng Li <Sunpeng.Li@amd.com> Acked-by:
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Harry Wentland authored
[Why & How] Remove dead code. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Block periods that are too short as they have the potential to currently cause hangs in other firmware components on the system. [How] Update the threshold, mostly targeting a block of 4k and downscaling. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Allows finer control and tuning for debug and profiling. [How] Add the debug option into DC. The default remains the same as before for now. Reviewed-by:
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Aric Cyr authored
This version brings along the following: - Correct way to find OPP index - Unify DC logging for BW Alloc - Add height granularity limitation for dsc slice height calculation Acked-by:
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Alvin Lee authored
[Description] For pipe harvesting cases we cannot rely on array index to get the correct OPP instance, we must loop through each instance to find the correct one. Reviewed-by:
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Mustapha Ghaddar authored
[WHY] To keep all logging within DC unified [HOW] Use the standard DC Logging functions Reviewed-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Mike Hsieh authored
[WHY] eDP add new limitation for Y granularity for selected update feature. DSC does not include this limitation while calculating slice height. [HOW] Add new limitation while looking for DSC slice height. Reviewed-by:
Cruise Hung <Cruise.Hung@amd.com> Acked-by:
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Perry Yuan authored
If some invalid workload types exposed by the power profile sysfs node, it will be failed to set the unsuported profiles. So we can skip to show the invalid workload type in the profiles list to avoid that failure happen. Acked-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Perry Yuan <perry.yuan@amd.com> Signed-off-by:
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Perry Yuan authored
Capped and Uncapped workload types are supported, each workload type has different performance thresholds and pstate conditions. * capped mode is used by power centric workload * uncapped mode is used by perf centric workload Acked-by:
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