- 01 Apr, 2015 40 commits
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Joshua Kinard authored
On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI buses attached to the Xtalk bus. The current code will stop counting PCI buses after it finds the first one. If one installs the optional PCI cardcage ("shoebox") into these systems, because of the order of the Xtalk widgets, the current PCI code will find the cardcage first, and fail to detect the BaseIO PCI devices, which are on a higher Xtalk widget ID. This patch adds the hooks needed for resolving this issue in the IP27 PCI code (in a later patch). Verified on both an SGI Onyx2 and an SGI Octane. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9074/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Joe Perches authored
Use the normal return values for bool functions Signed-off-by: Joe Perches <joe@perches.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9640/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Martin authored
When hardware checksum generation is switched on the checksum generation was only being signalled to the hardware correctly in Big Endian mode. Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9634/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Martin authored
The octeon crypto co-processor expects values to be big endian. Wrap the data transfers with cpu_to_be64() and be64_to_cpu() transformations. This passes for all the MD5 test vectors in crypto/testmgr.h Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9631/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Martin authored
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9635/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Martin authored
64 bit access is unaffected but for 32 bit access, swap high and low words. Similarly for 16 bit access, reverse the order of the four possible words, and for 8 bit access reverse the order of byte accesses. Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9630/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Martin authored
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9629/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Martin authored
Although the proper way to do this for bitfields would be to use the macro that Ralf has provided, this is a little easier to understand as a diff. Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9628/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
So let's remove everything that only makes sense for kernel modules. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Joshua Kinard authored
This allows the kernel to correctly detect an R16000 MIPS CPU on systems that have those. Otherwise, such systems will detect the CPU as an R14000, due to similarities in the CPU PRId value. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9092/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Andrew Bresticker authored
As an alternative to the "clock-frequency" property, allow the GIC timer operating clock to be specified in the device-tree instead. This is useful on systems which use common clock or where the GIC is not fixed to a particular frequency and is instead, for example, derived from the CPU clock. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9309/
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Chen Jie authored
Computing sum introduces true data dependency. This patch removes some true data depdendencies, hence increases instruction level parallelism. This patch brings up to 50% csum performance gain on Loongson 3a. One example about how this patch works is in CSUM_BIGCHUNK1: // ** original ** vs ** patch applied ** ADDC(sum, t0) ADDC(t0, t1) ADDC(sum, t1) ADDC(t2, t3) ADDC(sum, t2) ADDC(sum, t0) ADDC(sum, t3) ADDC(sum, t2) In the original implementation, each ADDC(sum, ...) depends on the sum value updated by previous ADDC(as source operand). With this patch applied, the first two ADDC operations are independent, hence can be executed simultaneously if possible. Another example is in the "copy and sum calculating chunk": // ** original ** vs ** patch applied ** STORE(t0, UNIT(0) ... STORE(t0, UNIT(0) ... ADDC(sum, t0) ADDC(t0, t1) STORE(t1, UNIT(1) ... STORE(t1, UNIT(1) ... ADDC(sum, t1) ADDC(sum, t0) STORE(t2, UNIT(2) ... STORE(t2, UNIT(2) ... ADDC(sum, t2) ADDC(t2, t3) STORE(t3, UNIT(3) ... STORE(t3, UNIT(3) ... ADDC(sum, t3) ADDC(sum, t2) With this patch applied, ADDC and the **next next** ADDC are independent. Signed-off-by: chenj <chenj@lemote.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9608/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Rafał Miłecki authored
[ralf@linux-mips.org: Fixed conflicts.] Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: Paul Walmsley <paul@pwsan.com> Patchwork: https://patchwork.linux-mips.org/patch/8665/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Aaro Koskinen authored
DSR-1000N board has two GPIO LEDs next to USB ports. Add support for them. [ralf@linux-mips.org: Resolved conflict due to the moving of the DTS files into vendor subdirectories.] Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9624/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Huacai Chen authored
This patch has no functional changes, it just to keep the assembler code to a minimum. Files and functions naming is borrowed from X86. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9616/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Huacai Chen authored
We found that TLB mismatch not only happens after kernel resume, but also happens during snapshot restore. So move it to the beginning of swsusp_arch_suspend(). Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: <stable@vger.kernel.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9621/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
With no I2C driver available, keeping the platform device registration makes no sense just as keeping the code to instantiage the I2C devices. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Bryan Wu <cooloney@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: linux-leds@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8203/
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Florian Fainelli authored
Since we are always sourcing arch/mips/bmips/Kconfig and there is no dependency on BMIPS_GENERIC, we will offer building BMIPS-related DTBs while this is not relevant for the other MIPS platforms. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jaedon.shin@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/9603/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer may cause parts of the DMA buffer to be prefetched into the RAC. To avoid possible coherency problems, flush the RAC upon DMA completion. Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
These got merged with the ath25 support after 4e7f7266 (MIPS: Remove unnecessary platform dma helper functions) had already removed them for all other platforms. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Michael Opdenacker authored
This removes the use of the IRQF_DISABLED flag from arch/mips/loongson/loongson-3/hpet.c It's a NOOP since 2.6.35. Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Cc: chenhc@lemote.com Cc: taohl@lemote.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9609/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Rafał Miłecki authored
There are two reasons for having this header in the common place: 1) Simplifying drivers that read NVRAM entries. We will be able to safely call bcm47xx_nvram_* functions without #ifdef-s. 2) Getting NVRAM driver out of MIPS arch code. This is needed to support BCM5301X arch which also requires this NVRAM driver. Patch for that will follow once we get is reviewed. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Paul Walmsley <paul@pwsan.com> Cc: linux-soc@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8619/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
With CONFIG_MIGRATION, the PFN of the migrating pages is stored in __swp_offset(), so we must have enough bits to store the largest possible PFN. OCTEON NUMA systems have 41 bits of physical address space, so with 4K pages (12-bits), we need at least 29 bits to store the PFN. The current width of 24-bits is too narrow, so expand it all the way out to 40-bits. This leaves the low order 16 bits as zero which does not interfere with any of the PTE bits. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9315/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Rafał Miłecki authored
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Paul Walmsley <paul@pwsan.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8662/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Rafał Miłecki authored
Also drop some unneeded memset-s. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Paul Walmsley <paul@pwsan.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8661/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Aaro Koskinen authored
On OCTEON the function is non-trivial and we can potentially even save some memory. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9338/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Andrew Bresticker authored
If a machine-specific hook is not implemented for restart, poweroff, or halt, fall back to halting secondary CPUs, disabling interrupts, and spinning. In the case of restart, attempt to restart the system via do_kernel_restart() (which will call any registered restart handlers) before halting. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9600/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Andrew Bresticker authored
Since cpu_wait() enables interrupts upon return, CPUs which have entered stop_this_cpu() may still end up handling interrupts. This can lead to the softlockup detector firing on a panic or restart/poweroff/halt. Just disable interrupts and spin to ensure nothing else runs on the CPU once it has entered stop_this_cpu(). Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9601/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Helmut Schaa authored
At least QCA955x can handle up to 256MBytes. Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Cc: linux-mips@linux-mips.org Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Helmut Schaa <helmut.schaa@googlemail.com> Patchwork: https://patchwork.linux-mips.org/patch/8738/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Delay slot emulation in the FPU emulator is the only kernel user of an executable stack, it is also very slow. Add a counter so we can see how many of these emulations are done. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8634/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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