- 05 Dec, 2022 2 commits
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Miquel Raynal authored
SPI NOR core changes: * Add support for flash reset using the dt reset-gpios property. * Update hwcaps.mask to include 8D-8D-8D read and page program ops when xSPI profile 1.0 table is defined. * Bypass zero erase size in spi_nor_find_best_erase_type(). * Fix select_uniform_erase to skip 0 erase size * Add generic flash driver. If a flash is not found in the flash_info array, fall back to the generic flash driver which is described solely by the flash's SFDP tables. * Fix the number of bytes for the dummy cycles in spi_nor_spimem_check_readop(). * Introduce SPI_NOR_QUAD_PP flag, as PP_1_1_4 is not SFDP discoverable. SPI NOR manufacturer drivers changes: * Spansion: - use PARSE_SFDP for s28hs512t, - add support for s28hl512t, s28hl01gt, and s28hs01gt. * Gigadevice: Replace default_init() with post_bfpt() for gd25q256. * Micron - ST: Enable locking for mt25qu256a. * Winbond: Add support for W25Q512NW-IQ. * ISSI: Use PARSE_SFDP and SPI_NOR_QUAD_PP. Fix merge conflict in the jedec,spi-nor bindings. Signed-off-by:Miquel Raynal <miquel.raynal@bootlin.com>
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Miquel Raynal authored
Raw NAND core changes: * Drop obsolete dependencies on COMPILE_TEST * MAINTAINERS: rectify entry for MESON NAND controller bindings * Drop EXPORT_SYMBOL_GPL for nanddev_erase() Raw NAND driver changes: * marvell: Enable NFC/DEVBUS arbiter * gpmi: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync * mpc5121: Replace NO_IRQ by 0 * lpc32xx_{slc,mlc}: - Switch to using pm_ptr() - Switch to using gpiod API * lpc32xx_mlc: Switch to using pm_ptr() * cadence: Support 64-bit slave dma interface * rockchip: Describe rk3128-nfc in the bindings * brcmnand: Update interrupts description in the bindings SPI-NAND driver changes: * winbond: - Add Winbond W25N02KV flash support - Fix flash identification Fix merge conflict with mtd tree regarding the brcm bindings. Signed-off-by:
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- 25 Nov, 2022 1 commit
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Jean Delvare authored
Since commit 0166dc11 ("of: make CONFIG_OF user selectable"), it is possible to test-build any driver which depends on OF on any architecture by explicitly selecting OF. Therefore depending on COMPILE_TEST as an alternative is no longer needed. It is actually better to always build such drivers with OF enabled, so that the test builds are closer to how each driver will actually be built on its intended target. Building them without OF may not test much as the compiler will optimize out potentially large parts of the code. In the worst case, this could even pop false positive warnings. Dropping COMPILE_TEST here improves the quality of our testing and avoids wasting time on non-existent issues. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by:
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- 24 Nov, 2022 2 commits
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Zheng Yongjun authored
Free 'info' upon remapping error to avoid a memory leak. Fixes: e644f7d6 ("[MTD] MAPS: Merge Lubbock and Mainstone drivers into common PXA2xx driver") Signed-off-by:
Zheng Yongjun <zhengyongjun3@huawei.com> [<miquel.raynal@bootlin.com>: Reword the commit log] Signed-off-by:
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Shang XiaoJing authored
del_mtd_device() will call of_node_put() to mtd_get_of_node(mtd), which is mtd->dev.of_node. However, memset(&mtd->dev, 0) is called before of_node_put(). As the result, of_node_put() won't do anything in del_mtd_device(), and causes the refcount leak. del_mtd_device() memset(&mtd->dev, 0, sizeof(mtd->dev) # clear mtd->dev of_node_put() mtd_get_of_node(mtd) # mtd->dev is cleared, can't locate of_node # of_node_put(NULL) won't do anything Fix the error by caching the pointer of the device_node. OF: ERROR: memory leak, expected refcount 1 instead of 2, of_node_get()/of_node_put() unbalanced - destroy cset entry: attach overlay node /spi/spi-sram@0 CPU: 3 PID: 275 Comm: python3 Tainted: G N 6.1.0-rc3+ #54 0d8a1edddf51f172ff5226989a7565c6313b08e2 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.15.0-0-g2dd4b9b3f840-prebuilt.qemu.org 04/01/2014 Call Trace: <TASK> dump_stack_lvl+0x67/0x83 kobject_get+0x155/0x160 of_node_get+0x1f/0x30 of_fwnode_get+0x43/0x70 fwnode_handle_get+0x54/0x80 fwnode_get_nth_parent+0xc9/0xe0 fwnode_full_name_string+0x3f/0xa0 device_node_string+0x30f/0x750 pointer+0x598/0x7a0 vsnprintf+0x62d/0x9b0 ... cfs_overlay_release+0x30/0x90 config_item_release+0xbe/0x1a0 config_item_put+0x5e/0x80 configfs_rmdir+0x3bd/0x540 vfs_rmdir+0x18c/0x320 do_rmdir+0x198/0x330 __x64_sys_rmdir+0x2c/0x40 do_syscall_64+0x37/0x90 entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: 00596576 ("mtd: core: clear out unregistered devices a bit more") Signed-off-by:Shang XiaoJing <shangxiaojing@huawei.com> [<miquel.raynal@bootlin.com>: Light reword of the commit log] Signed-off-by:
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- 22 Nov, 2022 2 commits
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Sudip Mukherjee authored
SFDP table of some flash chips do not advertise support of Quad Input Page Program even though it has support. Use flags and add hardware cap for these chips. Signed-off-by:
Sudip Mukherjee <sudip.mukherjee@sifive.com> [tudor.ambarus@microchip.com: move pp setting in spi_nor_init_default_params] Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220920184808.44876-2-sudip.mukherjee@sifive.com
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Sudip Mukherjee authored
The datasheet of is25wp256 says it supports SFDP. Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Testing showed the flash using SPINOR_OP_READ_1_1_4_4B 0x6c, SPINOR_OP_PP_4B 0x12 and SPINOR_OP_BE_4K_4B 0x21 before enabling SFDP. After this patch, it parses the SFDP information and still uses the same opcodes. Set sector_size and n_sectors to zero as they will be discovered when parsing SFDP. Signed-off-by:
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- 21 Nov, 2022 13 commits
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Jae Hyun Yoo authored
Add support for Winbond W25Q512NW-IQ/IN Signed-off-by:
Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Michael Walle <michael@walle.cc> Link: https://www.winbond.com/resource-files/W25Q512NW%20RevB%2007192021.pdf Link: https://lore.kernel.org/r/20220716000643.3541839-2-quic_jaehyoo@quicinc.com
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Eliav Farber authored
mt25qu256a [1] uses the 4 bit Block Protection scheme and supports Top/Bottom protection via the BP and TB bits of the Status Register. BP3 is located in bit 6 of the Status Register. Tested on MT25QU256ABA8ESF-0SIT. [1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdfSigned-off-by:
Eliav Farber <farbere@amazon.com> Signed-off-by:
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Allen-KH Cheng authored
The number of bytes used by spi_nor_spimem_check_readop() may be incorrect for the dummy cycles. Since nor->read_dummy is not initialized before spi_nor_spimem_adjust_hwcaps(). We use both mode and wait state clock cycles instead of nor->read_dummy. Fixes: 0e30f472 ("mtd: spi-nor: add support for DTR protocol") Co-developed-by:
Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Signed-off-by:
Dhruva Gole <d-gole@ti.com> Tested-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20221031124633.13189-1-allen-kh.cheng@mediatek.com
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Yaliang Wang authored
When utilizing PARSE_SFDP to initialize the flash parameter, the deprecated initializing method spi_nor_init_params_deprecated() and the function spi_nor_manufacturer_init_params() within it will never be executed, which results in the default_init hook function will also never be executed. This is okay for 'D' generation of GD25Q256, because 'D' generation is implementing the JESD216B standards, it has QER field defined in BFPT, parsing the SFDP can properly set the quad_enable function. The 'E' generation also implements the JESD216B standards, and it has the same status register definitions as 'D' generation, parsing the SFDP to set the quad_enable function should also work for 'E' generation. However, the same thing can't apply to 'C' generation. 'C' generation 'GD25Q256C' implements the JESD216 standards, and it doesn't have the QER field defined in BFPT, since it does have QE bit in status register 1, the quad_enable hook needs to be tweaked to properly set the quad_enable function, this can be done in post_bfpt fixup hook. Fixes: 047275f7 ("mtd: spi-nor: gigadevice: gd25q256: Init flash based on SFDP") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Yaliang Wang <Yaliang.Wang@windriver.com> [tudor.ambarus@microchip.com: Update comment in gd25q256_post_bfpt] Signed-off-by:
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Jonathan Neuschäfer authored
It doesn't make sense to put "set" on its own line like that. Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by:
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Michael Walle authored
We don't have a database entry for the generic SPI-NOR flash driver and thus we don't have a JEDEC ID to print. Print the (cached) JEDEC ID instead. Signed-off-by:
Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20220810220654.1297699-8-michael@walle.cc
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Michael Walle authored
Our SFDP parsing is everything we need to support all basic operations of a flash device. If the flash isn't found in our in-kernel flash database, gracefully fall back to a driver described solely by its SFDP tables. Signed-off-by:
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Michael Walle authored
4bait will set the erase size to 0 if there is no corresponding opcode for the 4byte erase. Fix spi_nor_select_uniform_erase to skip the 0 erase size to avoid mtd device registration failure cases. Reported-by:
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Michael Walle authored
sfdp.h should only contain constants related to the JEDEC SFDP specification(s). Signed-off-by:
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Michael Walle authored
At the moment, we print the JEDEC ID that is stored in our database. The generic flash support won't have such an entry in our database. To find out the JEDEC ID later we will have to cache it. There is also another advantage: If the flash is found in the database, the ID could be truncated because the ID of the entry is used which can be shorter. Some flashes still holds valuable information in the bytes after the JEDEC ID and come in handy during debugging of when coping with INFO6() entries. These are not accessible for now. Save a copy of the ID bytes after reading and display it via debugfs. Signed-off-by:
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Michael Walle authored
The manufacturer may be optional when pure SFDP flashes are supported. Hide the sysfs property if no manufacturer is set. Signed-off-by:
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Michael Walle authored
Some non-jedec compliant flashes (like the Everspin flashes) don't have an ID at all. Hide the attribute in this case. Fixes: 36ac0228 ("mtd: spi-nor: add initial sysfs support") Signed-off-by:
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Alexander Sverdlin authored
Erase can be zeroed in spi_nor_parse_4bait() or spi_nor_init_non_uniform_erase_map(). In practice it happened with mt25qu256a, which supports 4K, 32K, 64K erases with 3b address commands, but only 4K and 64K erase with 4b address commands. Fixes: dc928431 ("mtd: spi-nor: fix erase_type array to indicate current map conf") Signed-off-by:
Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by:
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- 17 Nov, 2022 20 commits
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Hamish Martin authored
The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and a generic local bus controller (Device Bus Controller) that share common pins. With a board design that incorporates both a NAND flash and uses the Device Bus (in our case for an SRAM) accessing the Device Bus device fails unless the NfArbiterEn bit is set. Setting the bit enables arbitration between the Device Bus and the NAND flash. Since there is no obvious downside in enabling this for designs that don't require arbitration, we always enable it. Signed-off-by:
Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by:
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Lukas Bulwahn authored
Commit dd5c672d ("arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA") removes config ARCH_BCM4908 as config ARCH_BCMBCA has the same intent. Probably due to concurrent development, commit 002181f5 ("mtd: parsers: add Broadcom's U-Boot parser") introduces 'Broadcom's U-Boot partition parser' that depends on ARCH_BCM4908, but this use was not visible during the config refactoring from the commit above. Hence, these two changes create a reference to a non-existing config symbol. Adjust the MTD_BRCM_U_BOOT definition to refer to ARCH_BCMBCA instead of ARCH_BCM4908 to remove the reference to the non-existing config symbol ARCH_BCM4908. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by:
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Rob Herring authored
The schema for 'sercomm,scpart-id' is broken. The 'if' condition is never true because 'compatible' is in the parent node, not the child node the sub-schema applies to. The example passes as there are no constraints on additional/unevaluated properties. That's a secondary issue which is complicated due to nested partitions. Drop the if/then schema and the unnecessary 'allOf' so that the 'sercomm,scpart-id' property is at least defined. Cc: Mikhail Zhilkin <csharper2005@gmail.com> Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Miquel Raynal authored
As recently requested by the binding maintaines, let's use 4 spaces in the examples. Signed-off-by:
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Miquel Raynal authored
Setting an object type is redundant when a reference is made, so drop these useless lines. Signed-off-by:
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Miquel Raynal authored
In most cases we try to avoid it but in some cases this is needed. Clarify why by adding a small comment. Signed-off-by:
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Miquel Raynal authored
The aim of MTD nvmem-cells is to treat MTD partitions as NVMEM providers. Hence, MTD partition properties are valid here. Let's reference mtd/partition.yaml which gives us a chance to drop "additionalProperties: true" in favor of "unevaluatedProperties: false". Signed-off-by:
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Miquel Raynal authored
Memory mapped devices such as parallel NOR flash could make use of the 'ranges' property to translate a nvmem 'reg' cell address to a CPU address but in practice there is no upstream user nor any declaration of this property being valid in this case yet, leading to a warning when constraining a bit more the schema: .../mtd/partitions/nvmem-cells.example.dtb: calibration@f00000: Unevaluated properties are not allowed ('ranges' was unexpected) So let's drop the property from the example, knowing that someone might actually properly define it some day. Signed-off-by: -
Miquel Raynal authored
As described in dd638202 ("dt-bindings: mtd: partitions: add additional example for qcom,smem-part"), the aim of documenting the subnodes was to be able to declare nvmem cells. Hence, the partition property does not really apply directly here, let's instead reference nvmem-cells.yaml first. Signed-off-by:
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Miquel Raynal authored
Parser compatibles cannot be used anywhere, and the list is limited. In order to constrain this list, enumerate them all under the top "partitions" subnode. New parsers will have to add their own compatible here as well. Signed-off-by:
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Miquel Raynal authored
The memory mapped MTD devices also share a lot with all the other MTD devices, so let's share the properties by referencing mtd.yaml. We can then drop mentioning the properties, to the cost of mentioning the possible "sram" node name prefix. Signed-off-by:
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Miquel Raynal authored
When redefining common properties does not bring any additional information, just drop them from the SPI-NOR bindings because these properties already are definied in mtd.yaml. Signed-off-by:
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Miquel Raynal authored
Copy-paste an existing DT node to ensure the dt_binding_check target would catch any unforeseen difference. Signed-off-by:
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Miquel Raynal authored
The chip node name in this driver is expected to be different and should be prefixed with onenand instead of the regular "flash" string, so mention it. Signed-off-by:
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Miquel Raynal authored
Defining partitions as subnodes of the controller has been deprecated long time ago, but unlike having partitions within the controller node, having an enveloppe named "partitions" (which is not itself within a chip subnode) is not that common, so keep this deprecated definition in this file. Signed-off-by:
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Miquel Raynal authored
In almost all the schema mentioning a NAND chip child node, the name of the subnode contains a single index number. In practice there are currently no controller supporting more than 8 cs so even the [a-f] numbers are not needed. But let's be safe and limit the number of touched files by just allow a single number everywhere, so in practice up to 16 CS at most. This value can anyway be limited in each schema. Signed-off-by:
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Miquel Raynal authored
generic files, so let's drop these properties from the individual NAND controller bindings when no additional information is provided rather than the possible presence of the property. Signed-off-by:
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Miquel Raynal authored
A NAND chip is an MTD device. mtd.yaml already defines many useful and relevant properties, let's reference this file here to get access to these additional property definitions. Signed-off-by:
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Miquel Raynal authored
There is already a real partitions.yaml file, so assuming everybody knows hot to read yaml schema now, this text file is no longer needed, so drop it. Depending on the situation, the lines referring to this file are either dropped or edited to point to mtd.yaml which includes partition{,s}.yaml. Signed-off-by: -
Miquel Raynal authored
Over time the various ways to define MTD partitions has evolved. Most of the controllers support several different bindings. Let's define all possible choices in one file and mark the legacy ones deprecated. This way, we can just reference this file and avoid dupplicating these definitions. Signed-off-by:
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