- 24 Jan, 2023 4 commits
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Li Ma authored
To support new mes ip block Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Li Ma authored
The GC 11.0.4 needs load IMU to power up GFX before loads GFX firmware. Signed-off-by:
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Evan Quan authored
Add SMU13.0.0 AllowIHInterrupt message mapping. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Jonathan Kim authored
Rebase of driver has incorrect unconditional trap enablement for GFX11 when adding mes queues. Reported-by:
Graham Sider <graham.sider@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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- 19 Jan, 2023 26 commits
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Alex Deucher authored
Update to the latest launched dGPUs. Link: https://www.amd.com/en/graphics/radeon-rx-graphics Link: https://www.amd.com/en/graphics/amd-radeon-rx-laptopsReviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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ye xingchen authored
resource.h is included more than once. Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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Marek Olšák authored
For computing PCIe bandwidth in userspace and troubleshooting PCIe bandwidth issues. Note that this intentionally fills holes and padding in drm_amdgpu_info_device. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20790Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Pierre-Eric Pelloux-Prayer authored
This allows to correlate the infos printed by /sys/kernel/debug/dri/n/amdgpu_gem_info to the ones found in /proc/.../fdinfo and /sys/kernel/debug/dma_buf/bufinfo. Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Tao Zhou authored
Fix the following compile warning: drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:53:24: warning: unused function 'get_umc_v6_7_channel_index' [-Wunused-function] static inline uint32_t get_umc_v6_7_channel_index(struct amdgpu_device *adev, ^ 1 warning generated. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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YiPeng Chai authored
Optimize sdma ras block initialization code for sdma v4_0. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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Arnd Bergmann authored
Some of the data structures are hidden when CONFIG_DRM_AMD_DC_DCN is disabled, which leads to a link failure: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:234:21: error: 'union hdmi_encoded_link_bw' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] 234 | const union hdmi_encoded_link_bw hdmi_encoded_link_bw) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:234:42: error: parameter 2 ('hdmi_encoded_link_bw') has incomplete type 234 | const union hdmi_encoded_link_bw hdmi_encoded_link_bw) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:232:17: error: function declaration isn't a prototype [-Werror=strict-prototypes] 232 | static uint32_t intersect_frl_link_bw_support( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c: In function 'get_active_converter_info': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:1126:76: error: storage size of 'hdmi_encoded_link_bw' isn't known 1126 | union hdmi_encoded_link_bw hdmi_encoded_link_bw; | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:1130:101: error: 'struct <anonymous>' has no member named 'MAX_ENCODED_LINK_BW_SUPPORT' 1130 | hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT); There is probably no need to hide the data structure, and removing the #ifdef makes it build cleanly. Fixes: d5a43956 ("drm/amd/display: move dp capability related logic to link_dp_capability") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Arnd Bergmann authored
gcc-13 notices a mismatch between the return type of dp_retrieve_lttpr_cap() and the returned value: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c: In function 'dp_retrieve_lttpr_cap': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:1465:24: error: implicit conversion from 'enum <anonymous>' to 'enum dc_status' [-Werror=enum-conversion] 1465 | return false; | ^~~~~ Change the value to an actual dc_status code and remove the bogus initialization that was apparently meant to get returned here. Fixes: b473bd5f ("drm/amd/display: refine wake up aux in retrieve link caps") Signed-off-by: -
YiPeng Chai authored
Add sdma ras function on sdma v6_0_3. Signed-off-by:
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Acked-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Acked-by:
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Mario Limonciello authored
Laptops with APUs from a variety of manufacturers and generations show a warning about a missing PSP runtime database. As it's not required for PSP to dump this database into framebuffer, decrease messages about it missing to debug. Reviewed-by:
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Mario Limonciello authored
Currently plugging in a USB-C device that issues an HPD will emit a warning level message `DP Alt mode state on HPD: %d`. This is needlessly noisy for most people, decrease it to debug so that it can be turned on by dynamic debug as needed. Reviewed-by:
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Alex Deucher authored
Only VCN0 supports AV1. Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Alex Deucher authored
Only VCN0 supports AV1. Reviewed-by:
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Alex Deucher authored
Only VCN0 supports AV1. Reviewed-by:
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Alex Deucher authored
Only VCN0 supports AV1. Reviewed-by:
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Mario Limonciello authored
Raphael launched in 2022 but was missed to add to this table. Reviewed-by:
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Mario Limonciello authored
Mendocino launched in 2023 and uses the new naming scheme for APU processors. Link: https://community.amd.com/t5/corporate/announcing-new-model-numbers-for-2023-mobile-processors/ba-p/543985Reviewed-by:
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Mario Limonciello authored
These products have launched, so add matching codenames. Also AMD has announced that both of these products have new refresh variants that launch in 2023 using the new naming scheme, so add that information. Link: https://community.amd.com/t5/corporate/announcing-new-model-numbers-for-2023-mobile-processors/ba-p/543985Reviewed-by:
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Mario Limonciello authored
MP0 version is useful to know to figure out which firmware is intended for a platform. Add a column for all supported APUs. v2: squash in column fix (Mario) Reviewed-by:
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Lang Yu authored
Always enable multipipe policy on ASICs with GC VERSION > 9.0.0 instead of MEC number > 1. This will allow multipipe policy on ASICs with one MEC, e.g., gfx11 APUs. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Lang Yu authored
There is only one MEC on these APUs. Signed-off-by:
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Hamza Mahfooz authored
Currently, we run into a number of WARN()s when attempting to unload the amdgpu driver (e.g. using "modprobe -r amdgpu"). These all stem from calling drm_encoder_cleanup() too early. So, to fix this we can stop calling drm_encoder_cleanup() from amdgpu_dm_fini() and instead have it be called from amdgpu_dm_encoder_destroy(). Also, we don't need to free in amdgpu_dm_encoder_destroy() since mst_encoders[] isn't explicitly allocated by the slab allocator. Fixes: f74367e4 ("drm/amdgpu/display: create fake mst encoders ahead of time (v4)") Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Guilherme G. Piccoli authored
The HW model validation that guards the indirect SRAM checking in the VCN code path is redundant - there's no model that's not included in the switch, making it useless in practice [0]. So, let's remove this switch statement for good. [0] lore.kernel.org/amd-gfx/MN0PR12MB61013D20B8A2263B22AE1BCFE2C19@MN0PR12MB6101.namprd12.prod.outlook.com Suggested-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Guilherme G. Piccoli authored
This is an incredibly trivial fix, just for the sake of "aesthetical" organization of the defines. Some were space based, most were tab based and there was a lack of "alignment", now it's all the same and aligned. Cc: James Zhu <James.Zhu@amd.com> Cc: Lazar Lijo <Lijo.Lazar@amd.com> Cc: Leo Liu <leo.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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- 17 Jan, 2023 10 commits
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Leo Liu authored
The problem is that base sched hasn't been assigned yet at this moment, causing something like "ring=0" all the time from trace. mpv:cs0-3473 [002] ..... 129.047431: amdgpu_cs: ring=0, dw=48, fences=0 mpv:cs0-3473 [002] ..... 129.089125: amdgpu_cs: ring=0, dw=48, fences=0 mpv:cs0-3473 [002] ..... 129.130987: amdgpu_cs: ring=0, dw=48, fences=0 mpv:cs0-3473 [002] ..... 129.172478: amdgpu_cs: ring=0, dw=48, fences=0 Fixes: 4624459c ("drm/amdgpu: add gang submit frontend v6") Signed-off-by:
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Stanley.Yang authored
There is xgmi3x16 pcs error status for aldebaran, driver should check xgmi3x16 pcs error status field instead of gopx16 pcs error status field. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Stanley.Yang authored
The pcs error count should be determined by PCS ERROR status and PCS ERROR MASK registers, only PCS ERROR status register can not refect error counts accurately. Changed from V1: remove clean noncorrectable mask registers optimize query pcs error status Changed from V2: remove check mask_value bits correct set value corresponding bit Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Christian König authored
It can be that neither fence were initialized when we run out of UVD streams for example. v2: fix typo breaking compile Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2324Signed-off-by:
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YiPeng Chai authored
Use gfx ras common initialization interface to initialize gfx ras block. V2: Update function call due to amdgpu_gfx_ras_sw_init interface changes. Signed-off-by:
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Thomas Zimmermann authored
Align a closing brace and remove trailing whitespaces. No functional changes. Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by:
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Joshua Ashton authored
The YCC conversion matrix for RGB -> COLOR_SPACE_YCBCR2020_TYPE is missing the values for the fourth column of the matrix. The fourth column of the matrix is essentially just a value that is added given that the color is 3 components in size. These values are needed to bias the chroma from the [-1, 1] -> [0, 1] range. This fixes color being very green when using Gamescope HDR on HDMI output which prefers YCC 4:4:4. Fixes: 40df2f80 ("drm/amd/display: color space ycbcr709 support") Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
Joshua Ashton <joshua@froggi.es> Signed-off-by:
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Joshua Ashton authored
Code in get_output_color_space depends on knowing the pixel encoding to determine whether to pick between eg. COLOR_SPACE_SRGB or COLOR_SPACE_YCBCR709 for transparent RGB -> YCbCr 4:4:4 in the driver. v2: Fixed patch being accidentally based on a personal feature branch, oops! Fixes: ea117312 ("drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded") Reviewed-by:
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Deepak R Varma authored
Use swap() helper macro instead of open coded swap instructions. The change also facilitates code cleanup and realignment for improved readability. Issue identified using swap.cocci Coccinelle semantic patch script. Signed-off-by:
Deepak R Varma <drv@mailo.com> Signed-off-by:
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Deepak R Varma authored
For bit mask addition, it is recommended to use or operator "|" instead of numerical addition as the former is quicker and cleaner. Change suggested by orplus.cocci Coccinelle semantic patch. Reviewed-by:
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