- 30 Apr, 2024 6 commits
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Rodrigo Siqueira authored
Drop unnecessary semicolon that can create a problem of double semicolon in some compilers. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
This commit add some DPCX IRQ types. Signed-off-by:
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Rodrigo Siqueira authored
In the DCN20 resource initialization, ensure that DMCUB support starts configured as true. Signed-off-by:
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Rodrigo Siqueira authored
This commit adds, updates, and removes some of the comments used in the DC code. Signed-off-by:
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Philip Yang authored
RDMA device with limited scatter-gather ability requires contiguous VRAM buffer allocation for RDMA peer direct support. Add a new KFD alloc memory flag and store as bo alloc flag AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS. When pin this bo to export for RDMA peerdirect access, this will set TTM_PL_FLAG_CONTIFUOUS flag, and ask VRAM buddy allocator to get contiguous VRAM. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Ma Jun authored
Assign value to clock to fix the warning below: "Using uninitialized value res. Field res.clock is uninitialized" Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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- 26 Apr, 2024 34 commits
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Nathan Chancellor authored
-Wframe-larger-than=2048 is a part of both CFLAGS and CFLAGS_REMOVE for dml2_core_dcn4_calcs.o, which means that it ultimately gets removed altogether for 64-bit targets, as 2048 is the default FRAME_WARN value for 64-bit platforms, resulting in no -Wframe-larger-than coverage for this file. Remove -Wframe-larger-than from CFLAGS_REMOVE_dml2_core_dcn4_calcs.o and move to $(frame_warn_flag) for CFLAGS_dml2_core_dcn4_calcs.o, as that accounts for the fact that -Wframe-larger-than may need to be larger than 2048 in certain situations, such as when the sanitizers are enabled. Fixes: 00c39110 ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
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Nathan Chancellor authored
When building with tip of tree Clang, there are some new instances of -Wframe-larger-than from the new display code (which become fatal with CONFIG_WERROR=y): drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:754:6: error: stack frame size (2488) exceeds limit (2048) in 'dml2_core_shared_mode_support' [-Werror,-Wframe-larger-than] 754 | bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params) | ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:9834:6: error: stack frame size (2152) exceeds limit (2048) in 'dml2_core_shared_mode_programming' [-Werror,-Wframe-larger-than] 9834 | bool dml2_core_shared_mode_programming(struct dml2_core_calcs_mode_programming_ex *in_out_params) | ^ 2 errors generated. These warnings do not occur when CONFIG_K{A,C,M}SAN are disabled, so add $(frame_warn_flag) to dml2_core_shared.o's CFLAGS, which was added in commit 6740ec97 ("drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml2") to account for this situation. Fixes: 00c39110 ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by: -
Srinivasan Shanmugam authored
This commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc` function. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Fixes: 70839da6 ("drm/amd/display: Add new DCN401 sources") Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Add miscellaneous changes to enable DCN401 init Signed-off-by:
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Aurabindo Pillai authored
Update macros to cover DCN 4.0.1. Signed-off-by:
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Aurabindo Pillai authored
Update for DCN 4.0.1. Signed-off-by:
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Aurabindo Pillai authored
Expose linear modifier definitions for use with DCN401 Signed-off-by:
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Aurabindo Pillai authored
Remove a duplicate definition of an SPL related enum transform.h Since its used in SPL, it has been moved to its own header. Signed-off-by:
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Aurabindo Pillai authored
Add initial support for DCN 4.0.1. Signed-off-by:
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Aurabindo Pillai authored
Update register headers. Signed-off-by:
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Aurabindo Pillai authored
GFX12 swizzle mode and GCC formats changed and is much simpler. Use a seperate function for the same. Changes: * Swizzle mode is now 3 bits only * DCC enablement doesn't come from tiling_flags, it is always set in modifiers * DCC max compressed block size of 128B Signed-off-by:
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Aurabindo Pillai authored
define new gfx12 uapi flags Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Add GFX12 swizzle mode definitions for use with DCN401 Signed-off-by:
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Rodrigo Siqueira authored
Add some missing HDCP registers to be used in DCN35. Signed-off-by:
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Jack Xiao authored
Update ADD_QUEUE interface for mes11 to support mes mapping legacy queue. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Jesse Zhang authored
Converting size from size_t to int may overflow. v2: keep reverse xmas tree order (Christian) Signed-off-by:
Jesse Zhang <jesse.zhang@amd.com> Reviewed-by:
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Jack Xiao authored
Add mes mapping legacy queue framework support. Signed-off-by:
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Tim Huang authored
Clear warning that uses uninitialized value fw_size. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This commit address some small code style issues in DC. Signed-off-by:
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Rodrigo Siqueira authored
This commit reorganizes the order in which some control registers are presented to make it easier to identify the operations based on the hardware doc. Signed-off-by:
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Rodrigo Siqueira authored
This commit removes some unnecessary code and makes the required adjustments to replace other parts of the code with a short option. Signed-off-by:
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Sunil Khatri authored
Do not dump the ip registers during driver reload in passthrough environment. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
Now we have two flags for contiguous VRAM buffer allocation. If the application request for AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, it would set the ttm place TTM_PL_FLAG_CONTIGUOUS flag in the buffer's placement function. This patch will change the default behaviour of the two flags. When we set AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS - This means contiguous is not mandatory. - we will try to allocate the contiguous buffer. Say if the allocation fails, we fallback to allocate the individual pages. When we setTTM_PL_FLAG_CONTIGUOUS - This means contiguous allocation is mandatory. - we are setting this in amdgpu_bo_pin_restricted() before bo validation and check this flag in the vram manager file. - if this is set, we should allocate the buffer pages contiguously. the allocation fails, we return -ENOSPC. v2: - keep the mem_flags and bo->flags check as is(Christian) - place the TTM_PL_FLAG_CONTIGUOUS flag setting into the amdgpu_bo_pin_restricted function placement range iteration loop(Christian) - rename find_pages with amdgpu_vram_mgr_calculate_pages_per_block (Christian) - Keep the kernel BO allocation as is(Christain) - If BO pin vram allocation failed, we need to return -ENOSPC as RDMA cannot work with scattered VRAM pages(Philip) v3(Christian): - keep contiguous flag handling outside of pages_per_block calculation - remove the hacky implementation in contiguous flag error handling code v4(Christian): - use any variable and return value for non-contiguous fallback v5: rebase to amd-staging-drm-next branch Signed-off-by:Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Suggested-by:
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Alex Hung authored
This fixes 29 UNINIT issues reported by Coverity. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Alex Hung authored
This fixes 49 UNINIT issues reported by Coverity. Reviewed-by:
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Alex Hung authored
This fixes 11 UNINIT issues reported by Coverity. Reviewed-by:
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Alex Hung authored
This fixes 1 PW.INCLUDE_RECURSION reported by Coverity. "./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h" includes itself: dc_types.h -> dal_types.h -> dc_types.h Acked-by:
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Alex Hung authored
[WHY] find_disp_cfg_idx_by_plane_id and find_disp_cfg_idx_by_stream_id returns an array index and they return -1 when not found; however, -1 is not a valid index number. [HOW] When this happens, call ASSERT(), and return a positive number (which is fewer than callers' array size) instead. This fixes 4 OVERRUN and 2 NEGATIVE_RETURNS issues reported by Coverity. Reviewed-by:
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Alex Hung authored
[WHY] resource_stream_to_stream_idx returns an array index and it return -1 when not found; however, -1 is not a valid array index number. [HOW] When this happens, call ASSERT(), and return a zero instead. This fixes an OVERRUN and an NEGATIVE_RETURNS issues reported by Coverity. Reviewed-by:
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Hersen Wu authored
[WHY] &mode_lib->mp.Watermark and &locals->Watermark are the same address. memcpy may lead to unexpected behavior. [HOW] memmove should be used. Reviewed-by:
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Alex Hung authored
[WHY] ENGINE_ID_UNKNOWN = -1 and can not be used as an array index. Plus, it also means it is uninitialized and does not need free audio. [HOW] Skip and return NULL. This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by:
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Alex Hung authored
pipe_ctx has a size of MAX_PIPES so checking its index before accessing the array. This fixes an OVERRUN issue reported by Coverity. Reviewed-by:
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Lancelot SIX authored
There are new control registers introduced in gfx10 used to configure hardware watchpoints triggered by SMEM instructions: SQ_WATCH{0,1,2,3}_{CNTL_ADDR_HI,ADDR_L}. Those registers work in a similar way as the TCP_WATCH* registers currently used for gfx9 and above. This patch adds support to program the SQ_WATCH registers for gfx10. The SQ_WATCH?_CNTL.MASK field has one bit more than TCP_WATCH?_CNTL.MASK, so SQ watchpoints can have a finer granularity than TCP_WATCH watchpoints. In this patch, we keep the capabilities advertised to the debugger unchanged (HSA_DBG_WATCH_ADDR_MASK_*_BIT_GFX10) as this reflects what both TCP and SQ watchpoints can do and both watchpoints are configured together. Signed-off-by:Lancelot SIX <lancelot.six@amd.com> Reviewed-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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Alex Hung authored
[WHAT] msg_id is used as an array index and it cannot be a negative value, and therefore cannot be equal to MOD_HDCP_MESSAGE_ID_INVALID (-1). [HOW] Check whether msg_id is valid before reading and setting. This fixes 4 OVERRUN issues reported by Coverity. Reviewed-by:
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