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  1. 08 Jul, 2015 1 commit
    • Chris Metcalf's avatar
      Make asm/word-at-a-time.h available on all architectures · a6e2f029
      Chris Metcalf authored
      Added the x86 implementation of word-at-a-time to the
      generic version, which previously only supported big-endian.
      
      Omitted the x86-specific load_unaligned_zeropad(), which in
      any case is also not present for the existing BE-only
      implementation of a word-at-a-time, and is only used under
      CONFIG_DCACHE_WORD_ACCESS.
      
      Added as a "generic-y" to the Kbuilds of all architectures
      that didn't previously have it.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@ezchip.com>
      a6e2f029
  2. 19 May, 2015 1 commit
  3. 17 Apr, 2015 1 commit
  4. 10 Dec, 2014 1 commit
  5. 13 Sep, 2014 1 commit
  6. 09 Feb, 2014 2 commits
    • Tim Chen's avatar
      locking/mcs: Allow architecture specific asm files to be used for contended case · ddf1d169
      Tim Chen authored
      This patch allows each architecture to add its specific assembly optimized
      arch_mcs_spin_lock_contended and arch_mcs_spinlock_uncontended for
      MCS lock and unlock functions.
      Signed-off-by: default avatarTim Chen <tim.c.chen@linux.intel.com>
      Cc: Scott J Norton <scott.norton@hp.com>
      Cc: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>
      Cc: AswinChandramouleeswaran <aswin@hp.com>
      Cc: George Spelvin <linux@horizon.com>
      Cc: Rik vanRiel <riel@redhat.com>
      Cc: Andrea Arcangeli <aarcange@redhat.com>
      Cc: MichelLespinasse <walken@google.com>
      Cc: Peter Hurley <peter@hurleysoftware.com>
      Cc: Andi Kleen <andi@firstfloor.org>
      Cc: Alex Shi <alex.shi@linaro.org>
      Cc: Dave Hansen <dave.hansen@intel.com>
      Cc: Tim Chen <tim.c.chen@linux.intel.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: "Figo.zhang" <figo1802@gmail.com>
      Cc: "Paul E.McKenney" <paulmck@linux.vnet.ibm.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Davidlohr Bueso <davidlohr.bueso@hp.com>
      Cc: Waiman Long <waiman.long@hp.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Matthew R Wilcox <matthew.r.wilcox@intel.com>
      Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
      Link: http://lkml.kernel.org/r/1390347382.3138.67.camel@schen9-DESKSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      ddf1d169
    • Tim Chen's avatar
      locking/mcs: Order the header files in Kbuild of each architecture in alphabetical order · b119fa61
      Tim Chen authored
      We perform a clean up of the Kbuid files in each architecture.
      We order the files in each Kbuild in alphabetical order
      by running the below script.
      
      for i in arch/*/include/asm/Kbuild
      do
              cat $i | gawk '/^generic-y/ {
                      i = 3;
                      do {
                              for (; i <= NF; i++) {
                                      if ($i == "\\") {
                                              getline;
                                              i = 1;
                                              continue;
                                      }
                                      if ($i != "")
                                              hdr[$i] = $i;
                              }
                              break;
                      } while (1);
                      next;
              }
              // {
                      print $0;
              }
              END {
                      n = asort(hdr);
                      for (i = 1; i <= n; i++)
                              print "generic-y += " hdr[i];
              }' > ${i}.sorted;
              mv ${i}.sorted $i;
      done
      Signed-off-by: default avatarTim Chen <tim.c.chen@linux.intel.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Matthew R Wilcox <matthew.r.wilcox@intel.com>
      Cc: AswinChandramouleeswaran <aswin@hp.com>
      Cc: Dave Hansen <dave.hansen@intel.com>
      Cc: "Paul E.McKenney" <paulmck@linux.vnet.ibm.com>
      Cc: Scott J Norton <scott.norton@hp.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: "Figo.zhang" <figo1802@gmail.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Waiman Long <waiman.long@hp.com>
      Cc: Peter Hurley <peter@hurleysoftware.com>
      Cc: Andrea Arcangeli <aarcange@redhat.com>
      Cc: Tim Chen <tim.c.chen@linux.intel.com>
      Cc: Alex Shi <alex.shi@linaro.org>
      Cc: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>
      Cc: Andi Kleen <andi@firstfloor.org>
      Cc: George Spelvin <linux@horizon.com>
      Cc: MichelLespinasse <walken@google.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Davidlohr Bueso <davidlohr.bueso@hp.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
      [ Fixed build bug. ]
      Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
      b119fa61
  7. 18 Dec, 2013 1 commit
  8. 25 Sep, 2013 1 commit
  9. 03 Sep, 2013 2 commits
  10. 30 Aug, 2013 1 commit
  11. 13 Nov, 2012 1 commit
  12. 17 Oct, 2012 1 commit
  13. 09 Oct, 2012 1 commit
  14. 03 Oct, 2012 1 commit
  15. 20 Sep, 2012 1 commit
  16. 18 Jul, 2012 1 commit
    • Chris Metcalf's avatar
      tile pci: enable IOMMU to support DMA for legacy devices · 41bb38fc
      Chris Metcalf authored
      This change uses the TRIO IOMMU to map the PCI DMA space and physical
      memory at different addresses.  We also now use the dma_mapping_ops
      to provide support for non-PCI DMA, PCIe DMA (64-bit) and legacy PCI
      DMA (32-bit).  We use the kernel's software I/O TLB framework
      (i.e. bounce buffers) for the legacy 32-bit PCI device support since
      there are a limited number of TLB entries in the IOMMU and it is
      non-trivial to handle indexing, searching, matching, etc.  For 32-bit
      devices the performance impact of bounce buffers should not be a concern.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      41bb38fc
  17. 28 Jun, 2012 1 commit
  18. 25 May, 2012 2 commits
    • Chris Metcalf's avatar
      arch/tile: support <asm/cachectl.h> header for cacheflush() syscall · cd6f32aa
      Chris Metcalf authored
      We already had a syscall that did some dcache flushing, but it was
      not used in practice.  Make it MIPS compatible instead so it can
      do both the DCACHE and ICACHE actions.  We have code that wants to
      be able to use the ICACHE flush mode from userspace so this change
      enables that.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      cd6f32aa
    • Chris Metcalf's avatar
      arch/tile: Allow tilegx to build with either 16K or 64K page size · d5d14ed6
      Chris Metcalf authored
      This change introduces new flags for the hv_install_context()
      API that passes a page table pointer to the hypervisor.  Clients
      can explicitly request 4K, 16K, or 64K small pages when they
      install a new context.  In practice, the page size is fixed at
      kernel compile time and the same size is always requested every
      time a new page table is installed.
      
      The <hv/hypervisor.h> header changes so that it provides more abstract
      macros for managing "page" things like PFNs and page tables.  For
      example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old
      HV_PAGE_SIZE_SMALL.  The various PFN routines have been eliminated and
      only PA- or PTFN-based ones remain (since PTFNs are always expressed
      in fixed 2KB "page" size).  The page-table management macros are
      renamed with a leading underscore and take page-size arguments with
      the presumption that clients will use those macros in some single
      place to provide the "real" macros they will use themselves.
      
      I happened to notice the old hv_set_caching() API was totally broken
      (it assumed 4KB pages) so I changed it so it would nominally work
      correctly with other page sizes.
      
      Tag modules with the page size so you can't load a module built with
      a conflicting page size.  (And add a test for SMP while we're at it.)
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      d5d14ed6
  19. 03 Nov, 2011 1 commit
  20. 03 Jun, 2011 1 commit
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  22. 04 Jun, 2010 1 commit
  23. 15 Jan, 2009 1 commit
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  25. 05 Aug, 2008 1 commit
  26. 07 Mar, 2007 1 commit
  27. 26 Sep, 2006 1 commit
  28. 18 Jun, 2006 1 commit