- 17 Apr, 2024 11 commits
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Alex Deucher authored
This reverts commit b5abd7f9. This change breaks DSC on 4k monitors at 144Hz over USB-C. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3254Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: Muhammad Ahmed <ahmed.ahmed@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Charlene Liu <charlene.liu@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Harry Wentland <harry.wentland@amd.com>
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Anthony Koo authored
Update dmub_cmd to manipulate SDP control in replay FSM, add command for panel_cntl, expand link rate enum, and increase the reserve byte. Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Sunil Khatri authored
Add vbios version in the devcoredump along with formatting the information with proper alignment. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Alex Deucher authored
Need to take the srbm_mutex and while we are here, use the helper function soc21_grbm_select(); Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Sung Joon Kim authored
Rework part of the modifications made to the power sequence and resource allocation logic. Reviewed-by:
Xi (Alex) Liu <xi.liu@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Sung Joon Kim authored
[why] IPS FSM requires Z10 flag to be enabled to do save and restore the registers properly. [how] Enable Z10 and use the correct function to determine Z10 capability Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Chaitanya Dhere authored
[Why] Pointer initialization and assignment for dml2_options is not done correctly. While this works for some compilers, others give an error. [How] Modify dc_state_create code to correctly initialize the dml2_opt pointer and pass it to dml2_create. Also update the code with correct derefrence operations. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] IPS ono sequence ordering differs based on the ASIC. [How] Detect the ASIC ID revision and set the boot option accordingly. Feed it through the DCN35 DMUB functions. Reviewed-by:
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Samson Tam authored
[Why] Adding support for chroma subsampling offset (cositing) in scaler calculations to adjust reference point where we determine post-scaling chroma value in YUV420 surfaces. [How] Add support for cositing options: NONE, LEFT and TOPLEFT Add debug option force_cositing and set default to TOPLEFT to maintain same behaviour as without offset support. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Charlene Liu authored
Limit the code change for ips enable to reduce the impact for now. Also exit_ips first before dc_power_down to avoid 0x9f. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Tested-by:
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Sung Joon Kim authored
To reduce the complexity of pipe resource allocation for different use-cases, now we search for any free pipe sequentially rather than from bottom up. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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- 12 Apr, 2024 17 commits
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Chris Park authored
[Why] DVI is TMDS signal like HDMI but without audio. Current signal check does not correctly reflect DVI clock programming. [How] Define a new signal check for TMDS that includes DVI to HDMI TMDS programming. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Sung Joon Kim authored
Need to update the power sequence to help prevent potential issues like multi-display or multi-plane. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following: - DCN10 fixes - DCN316 fixes - DML2 fixes - DWB fixes - Expanded FAMS support - Misc code style fixes - ODM fixes - VSC SDP fixes Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This commit makes some small adjustments in the dwb header. Acked-by:
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Felix Kuehling authored
Fix memory leak due to a leaked mmget reference on an error handling code path that is triggered when attempting to create KFD processes while a GPU reset is in progress. Fixes: 0ab2d753 ("drm/amdkfd: prepare per-process debug enable and disable") CC: Xiaogang Chen <xiaogang.chen@amd.com> Signed-off-by:
Felix Kuehling <felix.kuehling@amd.com> Tested-by:
Harish Kasiviswanthan <Harish.Kasiviswanthan@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Change DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT with DP_PHY_REPEATER_128B132B_RATES. Acked-by:
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Rodrigo Siqueira authored
Set OTG/OPTC parameters to 0 if something goes wrong on DCN10. Acked-by:
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Rodrigo Siqueira authored
Set OTG/OPTC parameter to 0 if failed to set DRR. Acked-by:
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Rodrigo Siqueira authored
Update DCN10 to use legacy fast update and ensure that the MPCC count is the same as the pipe_count. Acked-by:
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Rodrigo Siqueira authored
[WHY] DCN 1.0 is not ready for the P010 support. [HOW] 1. Set the P010 plan_cap of DCN 1.0 to be false. 2. Let the DM do the plan cap initialization of DCN 1.0. Reviewed-by:
Figo Wang <shen-hong.wang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Some of the resource capabilities for DCN201 and the debug default option are outdated. This commit just set some of the missing configurations for DCN201. Acked-by:
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Rodrigo Siqueira authored
This commit removes code that are not used by display anymore. Acked-by:
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Rodrigo Siqueira authored
Some of the includes used in the DC can be removed and others need to be update. This commit adjusts some of those headers in the display code. Acked-by:
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Rodrigo Siqueira authored
This commit just introduce some basic comments that helps to understand the overall behavior of some structs. Acked-by:
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Christian König authored
The majority of those where removed in the commit aed01a68 ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") But this one was missed because it's working on the resource and not the BO. Since we also no longer use a fake start address for visible BOs this will now trigger invalid mapping errors. v2: also remove the unused variable Signed-off-by:
Christian König <christian.koenig@amd.com> Fixes: aed01a68 ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") CC: stable@vger.kernel.org Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Jack Xiao authored
Set SDMAx_WATCHDOG_CNTL.QUEUE_HANG_COUNT registers to improve SDMA reliability. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luqmaan Irshad authored
Adding a new field for GPU Capacity to align the header with the host. Signed-off-by:
Luqmaan Irshad <Luqmaan.Irshad@amd.com> Acked-by:
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- 10 Apr, 2024 12 commits
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Yifan Zhang authored
This patch to differentiate external rev id for gfx 11.5.0. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Xiang Yang authored
the dram_clock_change_latency_us in dcn3_51_soc is initialized twice, so delete one of them. Acked-by:
Xiang Yang <xiangyang3@huawei.com> Signed-off-by:
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Simon Horman authored
The path to GPU documentation is Documentation/gpu rather than Documentation/GPU This appears to have been introduced by commit ba162ae7 ("Documentation/gpu: Introduce a simple contribution list for display code") Flagged by make htmldocs. Signed-off-by:
Simon Horman <horms@kernel.org> Signed-off-by:
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Erick Archer authored
This is an effort to get rid of all multiplications from allocation functions in order to prevent integer overflows [1] [2]. In this case, the memory allocated to store RADEONFB_CONN_LIMIT pointers to "drm_connector" structures can be avoided. This is because this memory area is never accessed. Also, in the kzalloc function, it is preferred to use sizeof(*pointer) instead of sizeof(type) due to the type of the variable can change and one needs not change the former (unlike the latter). At the same time take advantage to remove the "#if 0" block, the code where the removed memory area was accessed, and the RADEONFB_CONN_LIMIT constant due to now is never used. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/160 [2] Acked-by:
Erick Archer <erick.archer@outlook.com> Signed-off-by:
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Rodrigo Siqueira authored
DCN10 OPTC is used by other DCNs, and in some cases it might be useful to have V_TOTAL_REGS available. This commit add V_TOTAL_REGS as part of the TG field. Acked-by:
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Anthony Koo authored
- Add boot option to change the ONO powerup flow, impacting the order of power domains to power up or down first Acked-by:
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Qili Lu authored
This reverts commit b72a7e0f. It causes a dead loop in dml_prefetch_check. Reviewed-by:
Qili Lu <qili.lu@amd.com> Signed-off-by:
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George Shen authored
[Why] For video mode test pattern (i.e. test pattern disable), the call to rebuild test pattern params for the pipe is skipped. This causes dynamic disablement of test pattern to not work, as the test_pattern_params of the pipe will not be updated and retain the values of the previously enabled test pattern. [How] Rebuild test pattern params even when test pattern is video mode, allowing the pipe to have updated test_pattern_params values. Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Reviewed-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Zhongwei authored
[Why] OLED panels show no display for large vtotal timings. [How] Check if ss is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. DP_DTO adjustment is for edp only. Cc: stable@vger.kernel.org Reviewed-by:
Zhongwei <zhongwei.zhang@amd.com> Signed-off-by:
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Harry Wentland authored
The previous check for the is_vsc_sdp_colorimetry_supported flag for MST sink signals did nothing. Simplify the code and use the same check for MST and SST. Cc: stable@vger.kernel.org Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Acked-by:
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Harry Wentland authored
In order for display colorimetry to work correctly on DP displays we need to send the VSC SDP packet. We should only do so for panels with DPCD revision greater or equal to 1.4 as older receivers might have problems with it. Cc: stable@vger.kernel.org Cc: Joshua Ashton <joshua@froggi.es> Cc: Xaver Hugl <xaver.hugl@gmail.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Agustin Gutierrez <Agustin.Gutierrez@amd.com> Reviewed-by:
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Charlene Liu authored
[why] dwb was not POR previosly. now need to enable dwb in dml2. Limitation: HW DML assumes only one DWB one set of watermark for all 4 watermark sets one stream has one DWB only. WB scaling dml input has one set of scaling tap. (no chroma so far) needs to follow up Reviewed-by:
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