- 14 Aug, 2013 40 commits
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Anton Blanchard authored
Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Anton Blanchard authored
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Anton Blanchard authored
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Benjamin Herrenschmidt authored
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Anton Blanchard authored
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Anton Blanchard authored
We pass dma_window to of_parse_dma_window as a void * and then run through hoops to cast it back to a u32 array. In the process we lose endian annotation. Simplify it by just passing a __be32 * down. Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
Fix a couple of sparse warnings. Signed-off-by:
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Alistair Popple authored
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Alistair Popple <alistair@popple.id.au> Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
RTAS expects arguments in the call buffer to be big endian so we need to byteswap on little endian builds Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
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Alistair Popple authored
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Ian Munsie authored
On PowerPC the device tree is always big endian, but the CPU could be either, so add be32_to_cpu where appropriate and change the types of device tree data to __be32 etc to allow sparse to locate endian issues. Signed-off-by:
Ian Munsie <imunsie@au1.ibm.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
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Michael Neuling authored
When we have MMU on exceptions (POWER8) and a relocatable kernel, we need to branch from the initial exception vectors at 0x0 to up high where the kernel might be located. Currently we do this using the link register. Unfortunately this corrupts the link stack and instead we should use the count register. We did this for the syscall entry path in: 6a404806 powerpc: Avoid link stack corruption in MMU on syscall entry path but I stupidly forgot to do the same for other exceptions. This patch changes the initial exception vectors to use the count register instead of the link register when we need to branch up to the relocated kernel. I have a dodgy userspace test which loops calling a function that reads the PVR (mfpvr in userspace will be emulated by the kernel via the program check exception). On POWER8 and with CONFIG_RELOCATABLE=y, I get a ~10% performance improvement with my userspace test with this patch. Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Vasant Hegde authored
So far "/sys/devices/system/cpu/cpuX/topology/physical_package_id" was always default (-1) on ppc64 architecture. Now, some systems have an ibm,chip-id property in the cpu nodes in the device tree. On these systems, we now use this information to display physical_package_id. Signed-off-by:
Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by:
Shivaprasad G Bhat <sbhat@linux.vnet.ibm.com> Signed-off-by:
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Mike Qiu authored
changes for V4: - changes the type of frozen_pe_no from %d to %llu in pr_devel() 'pe_no' hasn't been defined, it should be an typo error, it should be 'frozen_pe_no'. Also '__func__' has missed in IODA_EEH_DBG(), For safety reasons, use pr_devel() directly, instead of use IODA_EEH_DBG() Signed-off-by:
Mike Qiu <qiudayu@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
This reverts commit c8db32c8. The commit breaks the build of all my 64-bit embedded configs. It looks like gcc-4.7.3 doesn't know about e5500. Additionally it incorrectly does -mcpu=e5500 on a config that has both e5500 and A2 support enabled. Signed-off-by:
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Paul Mackerras authored
Some systems have an ibm,chip-id property in the cpu nodes in the device tree. On these systems, we now use that to compute the cpu_core_mask (i.e. the set of core siblings) rather than looking at cache properties. Signed-off-by:
Paul Mackerras <paulus@samba.org> Tested-by:
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Paul Mackerras authored
This factors out the details of updating cpu_core_mask into a separate function, to make it easier to change how the mask is calculated later. This makes no functional change. Signed-off-by:
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Paul Mackerras authored
The denormalized exception handler (denorm_exception_hv) has a couple of bugs. If the CONFIG_PPC_DENORMALISATION option is not selected, or the HSRR1_DENORM bit is not set in HSRR1, we don't test whether the interrupt occurred within a KVM guest. On the other hand, if the HSRR1_DENORM bit is set and CONFIG_PPC_DENORMALISATION is enabled, we corrupt the CFAR and PPR. To correct these problems, this replaces the open-coded version of EXCEPTION_PROLOG_1 that is there currently, and that is missing the saving of PPR and CFAR values to the PACA, with an instance of EXCEPTION_PROLOG_1. This adds an explicit KVMTEST after testing whether the exception is one we can handle, and adds code to restore the CFAR on exit. Signed-off-by:
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Mark Brown authored
This is another file we can generate so add it to the list. Signed-off-by:
Mark Brown <broonie@linaro.org> Signed-off-by:
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James Yang authored
Load/store indexed instructions where the index register RA=R0, such as "lfdx f1,0,r3", are not illegal. Load/store indexed with update instructions where the index register RA=R0, such as "lfdux f1,0,r3", are invalid, and, to be consistent with existing math-emu behavior for other invalid instruction forms, will signal as illegal. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
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Kevin Hao authored
Instead of implementing an empty giveup_fpu() function for each 32bit processor type, replace them with an unique empty inline function. Signed-off-by:
Kevin Hao <haokexin@gmail.com> Signed-off-by:
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Kevin Hao authored
In the current kernel, the function flush_fp_to_thread() is not dependent on CONFIG_PPC_FPU. So most invocations of this function is not wrapped by CONFIG_PPC_FPU. Even through we don't really save the FPRs to the thread struct if CONFIG_PPC_FPU is not enabled, but there does have some runtime overhead such as the check for tsk->thread.regs and preempt disable and enable. It really make no sense to do that. So make it a nop when CONFIG_PPC_FPU is disabled. Also remove the wrapped #ifdef CONFIG_PPC_FPU when invoking this function. Signed-off-by:
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Kevin Hao authored
In commit c6e6771b(powerpc: Introduce VSX thread_struct and CONFIG_VSX) we add a invocation of flush_fp_to_thread() before copying the FPR or VSR to users. But we already invoke the flush_fp_to_thread() in this function. So remove one of them. Signed-off-by:
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Kevin Hao authored
We have split the math emulation into two parts. This makes it possible to just emulate the unimplemented floating point instructions on these boards. Signed-off-by:
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Kevin Hao authored
The only using of function disable_kernel_fp() was already dropped in the commit 5daf9071 (powerpc: merge align.c). Signed-off-by:
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Kevin Hao authored
For some SoC (such as the FSL BookE) even though there does have a hardware FPU, but not all floating point instructions are implemented. Unfortunately some versions of gcc do use these unimplemented instructions. Then we have to enable the math emulation to workaround this issue. It seems a little redundant to have the support to emulate all the floating point instructions in this case. So split the math emulation into two parts. One is for the SoC which doesn't have FPU at all and the other for the SoC which does have the hardware FPU and only need some special floating point instructions to be emulated. Signed-off-by:
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Kevin Hao authored
There are two invocations of do_mathemu() in traps.c. And the codes in these two places are almost the same. Introduce a locale function to eliminate the duplication. With this change we can also make sure that in program_check_exception() the PPC_WARN_EMULATED is invoked for the correctly emulated math instructions. Signed-off-by:
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Kevin Hao authored
By doing this we can make sure that the FPU state is only flushed to the thread struct when it is really needed. Signed-off-by:
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Kevin Hao authored
I got the following error on my t4240qds board. ntpd[2713]: unhandled signal 4 at 0fd5b448 nip 0fd5b448 lr 0fd5b424 code 30001 The root cause is that the float point instruction 'fsqrt' is used. But this instruction is not implemented on e6500 core. Even this does seem a gcc bug, I would like to enable the math emulation in the kernel to workaround this kind of issue. Signed-off-by:
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Paul Bolle authored
The Kconfig symbol 8XX_MINIMAL_FPEMU was removed in commit 968219fa ("powerpc/8xx: Remove 8xx specific "minimal FPU emulation""). But that commit didn't remove all code depending on that symbol. Do so now. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
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Kevin Hao authored
The math.c is only built when CONFIG_MATH_EMULATION is enabled. So the #ifdef check for CONFIG_MATH_EMULATION in it seems redundant. Drop all of them. Signed-off-by:
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Kevin Hao authored
The math.c is only built when CONFIG_MATH_EMULATION is enabled. So we would never get into the case that CONFIG_MATH_EMULATION is not defined in this file. Signed-off-by:
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Benjamin Herrenschmidt authored
Legacy UARTs can exist on PowerNV, memory-mapped ones on PCI or IO based ones on the LPC bus. Signed-off-by: -
Benjamin Herrenschmidt authored
Some machines might provide the console via a different mechanism such as direct access to a UART from Linux, in which case OPAL might not expose any console. In that case, the code would cause a NULL dereference. Signed-off-by: -
Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
The udbg_16550 code, which we use for our early consoles and debug backends was fairly messy. Especially for the debug consoles, it would re-implement the "high level" getc/putc/poll functions for each access method. It also had code to configure the UART but only for the straight MMIO method. This changes it to instead abstract at the register accessor level, and have the various functions and configuration routines use these. The result is simpler and slightly smaller code, and free support for non-MMIO mapped PIO UARTs, which such as the ones that can be present on a POWER 8 LPC bus. Signed-off-by:
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