- 14 Oct, 2022 5 commits
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Stephen Boyd authored
- Various clk rate range fixes - Drop clk rate range constraints on clk_put() (redux) * clk-rate-range: (28 commits) clk: mediatek: clk-mux: Add .determine_rate() callback clk: tests: Add tests for notifiers clk: Update req_rate on __clk_recalc_rates() clk: tests: Add missing test case for ranges clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d clk: Introduce the clk_hw_get_rate_range function clk: Zero the clk_rate_request structure clk: Stop forwarding clk_rate_requests to the parent clk: Constify clk_has_parent() clk: Introduce clk_core_has_parent() clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock clk: Add our request boundaries in clk_core_init_rate_req clk: Introduce clk_hw_init_rate_request() clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller clk: Change clk_core_init_rate_req prototype clk: Set req_rate on reparenting clk: Take into account uncached clocks in clk_set_rate_range() clk: tests: Add some tests for orphan with multiple parents clk: tests: Add tests for mux with multiple parents clk: tests: Add tests for single parent mux ...
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Jon Hunter authored
Commit 8c193f47 ("pwm: tegra: Optimize period calculation") updated the period calculation in the Tegra PWM driver and now returns an error if the period requested is less than minimum period supported. This is breaking PWM support on various Tegra platforms. For example, on the Tegra210 Jetson Nano platform this is breaking the PWM fan support and probing the PWM fan driver now fails ... pwm-fan pwm-fan: Failed to configure PWM: -22 pwm-fan: probe of pwm-fan failed with error -22 The problem is that the default parent clock for the PWM on Tegra210 is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. Fixes: 8c193f47 ("pwm: tegra: Optimize period calculation") Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20 Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3 Link: https://lore.kernel.org/r/20221010100046.6477-1-jonathanh@nvidia.comAcked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Kefeng Wang authored
There is an issue when build with older versions of binutils 2.27.0, arch/arm/mach-at91/pm_suspend.S: Assembler messages: arch/arm/mach-at91/pm_suspend.S:1086: Error: garbage following instruction -- `ldr tmp1,=0x00020010UL' Use UL() macro to fix the issue in assembly file. Fixes: 4fd36e45 ("ARM: at91: pm: add plla disable/enable support for sam9x60") Signed-off-by:
Kefeng Wang <wangkefeng.wang@huawei.com> Link: https://lore.kernel.org/r/20221012030635.13140-1-wangkefeng.wang@huawei.comSigned-off-by:
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Linus Walleij authored
These two clocks are now registered in the device tree as fixed clocks, causing a regression in the driver as the clock already exists with e.g. the name "pxo_board" as the MSM8660 GCC driver probes. Fix this by just not hard-coding this anymore and everything works like a charm. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: baecbda5 ("ARM: dts: qcom: msm8660: fix node names for fixed clocks") Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20221013140745.7801-1-linus.walleij@linaro.orgSigned-off-by:
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AngeloGioacchino Del Regno authored
Since commit 262ca38f ("clk: Stop forwarding clk_rate_requests to the parent"), the clk_rate_request is .. as the title says, not forwarded anymore to the parent: this produces an issue with the MediaTek clock MUX driver during GPU DVFS on MT8195, but not on MT8192 or others. This is because, differently from others, like MT8192 where all of the clocks in the MFG parents tree are of mtk_mux type, but in the parent tree of MT8195's MFG clock, we have one mtk_mux clock and one (clk framework generic) mux clock, like so: names: mfg_bg3d -> mfg_ck_fast_ref -> top_mfg_core_tmp (or) mfgpll types: mtk_gate -> mux -> mtk_mux (or) mtk_pll To solve this issue and also keep the GPU DVFS clocks code working as expected, wire up a .determine_rate() callback for the mtk_mux ops; for that, the standard clk_mux_determine_rate_flags() was used as it was possible to. This commit was successfully tested on MT6795 Xperia M5, MT8173 Elm, MT8192 Spherion and MT8195 Tomato; no regressions were seen. For the sake of some more documentation about this issue here's the trace of it: [ 12.211587] ------------[ cut here ]------------ [ 12.211589] WARNING: CPU: 6 PID: 78 at drivers/clk/clk.c:1462 clk_core_init_rate_req+0x84/0x90 [ 12.211593] Modules linked in: stp crct10dif_ce mtk_adsp_common llc rfkill snd_sof_xtensa_dsp panfrost(+) sbs_battery cros_ec_lid_angle cros_ec_sensors snd_sof_of cros_ec_sensors_core hid_multitouch cros_usbpd_logger snd_sof gpu_sched snd_sof_utils fuse ipv6 [ 12.211614] CPU: 6 PID: 78 Comm: kworker/u16:2 Tainted: G W 6.0.0-next-20221011+ #58 [ 12.211616] Hardware name: Acer Tomato (rev2) board (DT) [ 12.211617] Workqueue: devfreq_wq devfreq_monitor [ 12.211620] pstate: 40400009 (nZcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 12.211622] pc : clk_core_init_rate_req+0x84/0x90 [ 12.211625] lr : clk_core_forward_rate_req+0xa4/0xe4 [ 12.211627] sp : ffff80000893b8e0 [ 12.211628] x29: ffff80000893b8e0 x28: ffffdddf92f9b000 x27: ffff46a2c0e8bc05 [ 12.211632] x26: ffff46a2c1041200 x25: 0000000000000000 x24: 00000000173eed80 [ 12.211636] x23: ffff80000893b9c0 x22: ffff80000893b940 x21: 0000000000000000 [ 12.211641] x20: ffff46a2c1039f00 x19: ffff46a2c1039f00 x18: 0000000000000000 [ 12.211645] x17: 0000000000000038 x16: 000000000000d904 x15: 0000000000000003 [ 12.211649] x14: ffffdddf9357ce48 x13: ffffdddf935e71c8 x12: 000000000004803c [ 12.211653] x11: 00000000a867d7ad x10: 00000000a867d7ad x9 : ffffdddf90c28df4 [ 12.211657] x8 : ffffdddf9357a980 x7 : 0000000000000000 x6 : 0000000000000004 [ 12.211661] x5 : ffffffffffffffc8 x4 : 00000000173eed80 x3 : ffff80000893b940 [ 12.211665] x2 : 00000000173eed80 x1 : ffff80000893b940 x0 : 0000000000000000 [ 12.211669] Call trace: [ 12.211670] clk_core_init_rate_req+0x84/0x90 [ 12.211673] clk_core_round_rate_nolock+0xe8/0x10c [ 12.211675] clk_mux_determine_rate_flags+0x174/0x1f0 [ 12.211677] clk_mux_determine_rate+0x1c/0x30 [ 12.211680] clk_core_determine_round_nolock+0x74/0x130 [ 12.211682] clk_core_round_rate_nolock+0x58/0x10c [ 12.211684] clk_core_round_rate_nolock+0xf4/0x10c [ 12.211686] clk_core_set_rate_nolock+0x194/0x2ac [ 12.211688] clk_set_rate+0x40/0x94 [ 12.211691] _opp_config_clk_single+0x38/0xa0 [ 12.211693] _set_opp+0x1b0/0x500 [ 12.211695] dev_pm_opp_set_rate+0x120/0x290 [ 12.211697] panfrost_devfreq_target+0x3c/0x50 [panfrost] [ 12.211705] devfreq_set_target+0x8c/0x2d0 [ 12.211707] devfreq_update_target+0xcc/0xf4 [ 12.211708] devfreq_monitor+0x40/0x1d0 [ 12.211710] process_one_work+0x294/0x664 [ 12.211712] worker_thread+0x7c/0x45c [ 12.211713] kthread+0x104/0x110 [ 12.211716] ret_from_fork+0x10/0x20 [ 12.211718] irq event stamp: 7102 [ 12.211719] hardirqs last enabled at (7101): [<ffffdddf904ea5a0>] finish_task_switch.isra.0+0xec/0x2f0 [ 12.211723] hardirqs last disabled at (7102): [<ffffdddf91794b74>] el1_dbg+0x24/0x90 [ 12.211726] softirqs last enabled at (6716): [<ffffdddf90410be4>] __do_softirq+0x414/0x588 [ 12.211728] softirqs last disabled at (6507): [<ffffdddf904171d8>] ____do_softirq+0x18/0x24 [ 12.211730] ---[ end trace 0000000000000000 ]--- Fixes: 262ca38f ("clk: Stop forwarding clk_rate_requests to the parent") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221011135548.318323-1-angelogioacchino.delregno@collabora.comSigned-off-by:
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- 11 Oct, 2022 2 commits
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Maxime Ripard authored
We're recently encountered a regression due to the rates reported through the clk_notifier_data being off when changing parents. Let's add a test suite and a test to make sure that we do get notified and with the proper rates. Suggested-by:
Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221010-rpi-clk-fixes-again-v1-2-d87ba82ac404@cerno.techTested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
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Maxime Ripard authored
Commit cb1b1dd9 ("clk: Set req_rate on reparenting") introduced a new function, clk_core_update_orphan_child_rates(), that updates the req_rate field on reparenting. It turns out that that function will interfere with the clock notifying done by __clk_recalc_rates(). This ends up reporting the new rate in both the old_rate and new_rate fields of struct clk_notifier_data. Since clk_core_update_orphan_child_rates() is basically __clk_recalc_rates() without the notifiers, and with the req_rate field update, we can drop clk_core_update_orphan_child_rates() entirely, and make __clk_recalc_rates() update req_rate. However, __clk_recalc_rates() is being called in several code paths: when retrieving a rate (most likely through clk_get_rate()), when changing parents (through clk_set_rate() or clk_hw_reparent()), or when updating the orphan status (through clk_core_reparent_orphans_nolock(), called at registration). Updating req_rate on reparenting or initialisation makes sense, but we shouldn't do it on clk_get_rate(). Thus an extra flag has been added to update or not req_rate depending on the context. Fixes: cb1b1dd9 ("clk: Set req_rate on reparenting") Link: https://lore.kernel.org/linux-clk/0acc7217-762c-7c0d-45a0-55c384824ce4@samsung.com/ Link: https://lore.kernel.org/linux-clk/Y0QNSx+ZgqKSvPOC@sirena.org.uk/Reported-by:
Mark Brown <broonie@kernel.org> Suggested-by:
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- 04 Oct, 2022 10 commits
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Stephen Boyd authored
- Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - Support for Renesas VersaClock7 clock generator family * clk-baikal: clk: baikal-t1: Convert to platform device driver clk: baikal-t1: Add DDR/PCIe directly controlled resets support dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs clk: baikal-t1: Move reset-controls code into a dedicated module clk: baikal-t1: Add SATA internal ref clock buffer clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent clk: baikal-t1: Fix invalid xGMAC PTP clock divider clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD * clk-broadcom: clk: bcm: rpi: Add support for VEC clock clk: bcm: rpi: Handle pixel clock in firmware clk: bcm: rpi: Add support HEVC clock clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration clk: bcm2835: Round UART input clock up clk: bcm2835: Make peripheral PLLC critical * clk-vc5: clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: vc5: Use regmap_{set,clear}_bits() where appropriate clk: vc5: Check IO access results * clk-versaclock: clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings -
Stephen Boyd authored
- More devm helpers for fixed rate registration - Add Spreadtrum UMS512 SoC clk support - Various PXA168 clk driver fixes * clk-fixed-rate: clk: fixed-rate: add devm_clk_hw_register_fixed_rate clk: asm9260: use parent index to link the reference clock * clk-spreadtrum: clk: sprd: Add clocks support for UMS512 * clk-pxa: clk: pxa: add a check for the return value of kzalloc() clk: mmp: pxa168: control shared SDH bits with separate clock dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks clk: mmp: pxa168: add clocks for SDH2 and SDH3 dt-bindings: marvell,pxa168: add clock id for SDH3 clk: mmp: pxa168: fix GPIO clock enable bits clk: mmp: pxa168: add muxes for more peripherals clk: mmp: pxa168: fix incorrect parent clocks clk: mmp: pxa168: fix const-correctness clk: mmp: pxa168: add new clocks for peripherals dt-bindings: marvell,pxa168: add clock ids for additional dividers clk: mmp: pxa168: fix incorrect dividers clk: mmp: pxa168: add additional register defines * clk-ti: clk: davinci: cfgchip: Use dev_err_probe() helper clk: davinci: pll: fix spelling typo in comment MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER
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Stephen Boyd authored
Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner' and 'clk-imx' into clk-next * clk-rockchip: dt-bindings: clock: rockchip: change SPDX-License-Identifier dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML clk: rockchip: Add clock controller support for RV1126 SoC dt-bindings: clock: rockchip: Document RV1126 CRU clk: rockchip: Add dt-binding header for RV1126 clk: rockchip: Add MUXTBL variant * clk-renesas: clk: renesas: r8a779g0: Add EtherAVB clocks clk: renesas: r8a779g0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Add I2C clocks clk: renesas: r8a779g0: Add watchdog clock dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC clk: renesas: r8a779f0: Add MSIOF clocks clk: renesas: r9a09g011: Add IIC clock and reset entries clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks clk: renesas: r8a779f0: Add CMT clocks clk: renesas: r8a779f0: Add SDH0 clock * clk-microchip: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation * clk-allwinner: clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper clk: sunxi-ng: d1: Limit PLL rates to stable ranges * clk-imx: clk: imx: scu: fix memleak on platform_device_add() fails clk: imx93: add SAI IPG clk clk: imx93: add MU1/2 clock clk: imx93: switch to use new clk gate API clk: imx: add i.MX93 clk gate clk: imx: clk-composite-93: check white_list clk: imx: clk-composite-93: check slice busy dt-bindings: clock: imx93-clock: add more MU/SAI clocks dt-bindings: clock: imx8mm: don't use multiple blank lines clk: imx8mp: tune the order of enet_qos_root_clk
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Stephen Boyd authored
- Add resets for MediaTek MT8195 PCIe and USB - Remove DaVinci DM644x and DM646x clk driver support * clk-samsung: clk: samsung: MAINTAINERS: add Krzysztof Kozlowski clk: samsung: exynos850: Implement CMU_MFCMSCL domain clk: samsung: exynos850: Implement CMU_IS domain clk: samsung: exynos850: Implement CMU_AUD domain clk: samsung: exynos850: Style fixes clk: samsung: exynosautov9: add fsys1 clock support clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: correct register offsets of peric0/c1 clk: samsung: exynosautov9: add missing gate clks for peric0/c1 dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add fys0 clock definitions clk: samsung: exynos7885: Add TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 clk: samsung: exynos-clkout: Use of_device_get_match_data() * clk-mtk: (42 commits) clk: mediatek: add driver for MT8365 SoC clk: mediatek: Export required common code symbols clk: mediatek: Provide mtk_devm_alloc_clk_data dt-bindings: clock: mediatek: add bindings for MT8365 SoC clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks ... * clk-rm: clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x * clk-ast: clk: ast2600: BCLK comes from EPLL * clk-qcom: (97 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks ...
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Stephen Boyd authored
Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'clk-xilinx' into clk-next - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging * clk-ofnode: clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: tegra20: Fix refcount leak in tegra20_clock_init clk: tegra: Fix refcount leak in tegra114_clock_init clk: tegra: Fix refcount leak in tegra210_clock_init clk: sprd: Hold reference returned by of_get_parent() clk: berlin: Add of_node_put() for of_get_parent() clk: at91: dt-compat: Hold reference returned by of_get_parent() clk: qoriq: Hold reference returned by of_get_parent() clk: oxnas: Hold reference returned by of_get_parent() clk: st: Hold reference returned by of_get_parent() clk: tegra: Add missing of_node_put() clk: meson: Hold reference returned by of_get_parent() clk: nomadik: Add missing of_node_put() * clk-bindings: dt-bindings: clock: drop minItems equal to maxItems dt-bindings: clock: gpio-gate-clock: Convert to json-schema dt-bindings: clock: Move versaclock.h to dt-bindings/clock dt-bindings: clock: Move lochnagar.h to dt-bindings/clock * clk-cleanup: clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: nxp: fix typo in comment clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clkdev: Simplify devm_clk_hw_register_clkdev() function clkdev: Remove never used devm_clk_release_clkdev() clk: Remove never used devm_of_clk_del_provider() clk: pistachio: Fix initconst confusion clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data clk: do not initialize ret clk: remove extra empty line clk: Fix comment typo clk: move from strlcpy with unused retval to strscpy * clk-zynq: clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate clk: zynqmp: Check the return type zynqmp_pm_query_data clk: zynqmp: Add a check for NULL pointer clk: zynqmp: Replaced strncpy() with strscpy() clk: zynqmp: Fix stack-out-of-bounds in strncpy` clk: zynqmp: make bestdiv unsigned * clk-xilinx: clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: clocking-wizard: Update the compatible clk: clocking-wizard: Fix the reconfig for 5.2 clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs clk: clocking-wizard: Move clocking-wizard out dt-bindings: add documentation of xilinx clocking wizard
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Stephen Boyd authored
This PLL frequency needs a UL postfix to avoid compiler warnings on 32-bit architectures. Fixes: 184fdd87 ("clk: qcom: Add global clock controller driver for SM6375") Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
gcc_parent_data_15 and gcc_parent_map_15 are not used in this driver. Remove them. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20221003211438.25691-1-konrad.dybcio@somainline.org Fixes: 184fdd87 ("clk: qcom: Add global clock controller driver for SM6375") Signed-off-by:
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Christian Marangi authored
Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. .name is changed to the legacy pxo_board following how it's declared in other drivers. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220914144743.17369-2-ansuelsmth@gmail.comReviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Christian Marangi authored
Introduce (devm_)hw_register_mux_parent_data_table new API. We have basic support for clk_register_mux using parent_data but we lack any API to provide a custom parent_map. Add these 2 new API to correctly handle these special configuration instead of using the generic __(devm_)clk_hw_register_mux API. Signed-off-by:
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Stephen Boyd authored
Merge tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces display clock controllers are introduces for SM6115 and SM8450, and SC8280XP gains a GPU clock controller. MSM8909 and SM6375 gains global and SMD RPM clock controller drivers. The handling of GDSCs with PWRSTS_RET was fixed, to keep the GDSC on while powering down the parent supply. This solved retention issues during suspend of USB on sc7180/7280 and SC8280XP. SM6115 and QCM2260 are moved to reuse PLL configuration. SDM660 SDCC1 was moved to floor ops. Support for the APCS PLLs for IPQ8064, IPQ8074 and IPQ6018 was added/fixed. The MSM8996 CPU clocks was updated, with support for ACD clocks added. Support for SDM670 was added to the SDM845 Glbal clock controller and the RPMh clock controller driver. Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for MSM8660, MSM8916, MSM8939, MSM8960 global clock controllers, IPQ8064 LPASS clock controller and MSM8960 multimedia clock controller. Support for per-reset defined delay of was introduced. * tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (93 commits) clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375 clk: qcom: rpmhcc: add sdm670 clocks dt-bindings: clock: add rpmhcc bindings for sdm670 ...
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- 03 Oct, 2022 9 commits
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Clément Léger authored
Set the COMMON_CLK_LAN966X option as a tristate and switch from builtin_platform_driver() to module_platform_driver() to allow building and using this driver as a module. Signed-off-by:
Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220617103306.489466-1-clement.leger@bootlin.comSigned-off-by:
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Yihao Han authored
Replace `if (!pclk->param.csr_reg)` with `else` for simplification and add curly brackets according to the kernel coding style: "Do not unnecessarily use braces where a single statement will do." ... "This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches" Please refer to: https://www.kernel.org/doc/html/v5.17-rc8/process/coding-style.htmlSigned-off-by:
Yihao Han <hanyihao@vivo.com> Link: https://lore.kernel.org/r/20220408130617.14963-1-hanyihao@vivo.comSigned-off-by:
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Joel Stanley authored
This correction was made in the u-boot SDK recently. There are no in-tree users of this clock so the impact is minimal. Fixes: d3d04f6c ("clk: Add support for AST2600 SoC") Link: https://github.com/AspeedTech-BMC/u-boot/commit/8ad54a5ae15f27fea5e894cc2539a20d90019717Signed-off-by:
Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.auSigned-off-by:
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Stephen Boyd authored
This driver uses devm_platform_ioremap_resource() and thus depends on HAS_IOMEM. Add the Kconfig dependency to avoid build issues. Reported-by:
kernel test robot <lkp@intel.com> Cc: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Fixes: c822490f ("clk: clocking-wizard: Move clocking-wizard out") Link: https://lore.kernel.org/r/20221003202608.2611295-1-sboyd@kernel.orgSigned-off-by:
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Yang Yingliang authored
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220913031442.980720-1-yangyingliang@huawei.comSigned-off-by:
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Julia Lawall authored
Spelling mistake (triple letters) in comment. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/20220521111145.81697-42-Julia.Lawall@inria.frAcked-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
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Xiaoke Wang authored
kzalloc() is a memory allocation function which can return NULL when some internal memory errors happen. So it is better to check it to prevent potential wrong memory access. Signed-off-by:
Xiaoke Wang <xkernel.wang@foxmail.com> Link: https://lore.kernel.org/r/tencent_2B9817738F38B02844C245946EFF3B407E09@qq.comSigned-off-by:
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Matthias Fend authored
Update IDT VersaClock 5 driver to support 5P49V6975. The 5P49V6975 is a member of the VersaClock 6E family and supports four fractional dividers (FODs), five clock outputs and an internal oscillator. Signed-off-by:
Matthias Fend <matthias.fend@emfend.at> Link: https://lore.kernel.org/r/20220511053455.360335-2-matthias.fend@emfend.atReviewed-by:
Luca Ceresoli <luca@lucaceresoli.net> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Matthias Fend authored
The 5P49V6975 is a member of the VersaClock 6E family and supports four fractional dividers (FODs), five clock outputs and an internal oscillator. Signed-off-by:
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- 01 Oct, 2022 8 commits
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ye xingchen authored
Return the value of_clk_add_hw_provider() directly instead of storing it in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220906072322.337253-1-ye.xingchen@zte.com.cnSigned-off-by:
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Miaoqian Lin authored
pm_runtime_get_sync() will increment pm usage counter. Forgetting to putting operation will result in reference leak. Add missing pm_runtime_put_sync in some error paths. Fixes: 9ac33b0c ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.comReviewed-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Alex Helms authored
Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by:
Alex Helms <alexander.helms.jy@renesas.com> Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.comTested-by:
Saeed Nowshadi <saeed.nowshadi@amd.com> Signed-off-by:
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Alex Helms authored
Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220912183613.22213-2-alexander.helms.jy@renesas.comTested-by:
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Liang He authored
In ti_find_clock_provider(), of_find_node_by_name() will call of_node_put() for the 'from' argument, possibly putting the node one too many times. Let's maintain the of_node_get() from the previous search and only put when we're exiting the function early. This should avoid a misbalanced reference count on the node. Fixes: 51f661ef ("clk: ti: Add ti_find_clock_provider() to use clock-output-names") Signed-off-by:
Liang He <windhl@126.com> Link: https://lore.kernel.org/r/20220915031121.4003589-1-windhl@126.com [sboyd@kernel.org: Rewrite commit text, maintain reference instead of get again] Signed-off-by:
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Lin Yujun authored
No error handling is performed when platform_device_add() fails. Add error processing before return, and modified the return value. Fixes: 77d8f306 ("clk: imx: scu: add two cells binding support") Signed-off-by:
Lin Yujun <linyujun809@huawei.com> Link: https://lore.kernel.org/r/20220914033206.98046-1-linyujun809@huawei.comSigned-off-by:
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Lars-Peter Clausen authored
regmap_set_bits() and regmap_clear_bits() are variations of regmap_update_bits() that can be used if all bits of the mask have to be set to either 1 or 0 respectively. Update the versaclk driver to use regmap_set_bits() and regmap_clear_bits() where appropriate. This results in slightly more compact code and also makes the intention of the code clearer which can help with review. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20220719094637.844946-2-lars@metafoo.deReviewed-by:
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Lars-Peter Clausen authored
The devices of the versaclk clock generator family use an I2C control bus. IO access on an I2C bus can fail for various reasons. The driver currently ignores the return value of most IO operations. This results in silent failure. To avoid this check the return value and in case of an error abort the operation and propagate the error code to the caller. Signed-off-by:
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- 30 Sep, 2022 6 commits
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Fabien Parent authored
Add clock drivers for MT8365 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.comReported-by:
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Markus Schneider-Pargmann authored
To make clk-mt8365 compilable as a module there are a few function symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the functions. Signed-off-by:
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Markus Schneider-Pargmann authored
Provide a helper that replaces the kzalloc with devm_kzalloc so error handling gets easier. Signed-off-by:
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Fabien Parent authored
Add the clock bindings for the MediaTek MT8365 SoC. Signed-off-by:
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Andy Shevchenko authored
Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220623115719.52683-3-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
For the entire history of the devm_clk_release_clkdev() existence (since 2018) it was never used. Remove it for good. Signed-off-by:
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