- 30 Aug, 2013 40 commits
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Alex Deucher authored
No need to try the ring tests if starting the UVD block failed. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com>
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Alex Deucher authored
For powergating, we just need to re-init the registers, there is no need to restore the uvd BOs. This just adds needless work when powergating uvd for playback while the system is on. We only need to restore the uvd BOs on an actual resume from suspend or when the driver loads. This fixes multi-stream UVD playback on KB systems. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com>
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Sergey Senozhatsky authored
Commit a01c34f7 (radeon kms: do not flush uninitialized hotplug work) moved work initialisation phase to the last step of radeon_irq_kms_init(). Meelis Roos reported that this causes problems on his machine because drm_irq_install() uses hotplug work on r100. hotplug work flushed in radeon_irq_kms_fini(), with two possible cases: -- radeon_irq_kms_fini() call after successful radeon_irq_kms_init() -- radeon_irq_kms_fini() call after unsuccessful (or not called at all) radeon_irq_kms_init() The latter one causes flush work on uninitialised hotplug work. Move work initialisation before drm_irq_install(), but keep existing agreement to flush hotplug work in radeon_irq_kms_fini() only for `irq.installed' (successful radeon_irq_kms_init()) case. WARNING: CPU: 0 PID: 243 at kernel/workqueue.c:1378 __queue_work+0x132/0x16d() Call Trace: [<c12319b3>] ? dump_stack+0xa/0x13 [<c1022600>] ? warn_slowpath_common+0x75/0x8a [<c1031010>] ? __queue_work+0x132/0x16d [<c1031010>] ? __queue_work+0x132/0x16d [<c102269e>] ? warn_slowpath_null+0x1b/0x1f [<c1031010>] ? __queue_work+0x132/0x16d [<c103107b>] ? queue_work_on+0x30/0x40 [<f8aed3f3>] ? r100_irq_process+0x16d/0x1e6 [radeon] [<f8ae77cf>] ? radeon_driver_irq_preinstall_kms+0xc2/0xc5 [radeon] [<f8974d77>] ? drm_irq_install+0xb2/0x1ac [drm] [<f897604d>] ? drm_vblank_init+0x196/0x1d2 [drm] [<f8ae78d3>] ? radeon_irq_kms_init+0x33/0xc6 [radeon] [<f8aef35a>] ? r100_startup+0x1a3/0x1d6 [radeon] [<f8ad77c8>] ? radeon_ttm_init+0x26e/0x287 [radeon] [<f8aef752>] ? r100_init+0x2b3/0x309 [radeon] [<c118082e>] ? vga_client_register+0x39/0x40 [<f8ac535f>] ? radeon_device_init+0x54b/0x61b [radeon] [<f8ac40fd>] ? cail_mc_write+0x13/0x13 [radeon] [<f8ac6864>] ? radeon_driver_load_kms+0x82/0xda [radeon] [<f8978bbd>] ? drm_get_pci_dev+0x136/0x22d [drm] [<f8ac409b>] ? radeon_pci_probe+0x6c/0x86 [radeon] [<c112acf6>] ? pci_device_probe+0x4c/0x83 [<c11846c7>] ? driver_probe_device+0x80/0x184 [<c112a848>] ? pci_match_id+0x18/0x36 [<c1184837>] ? __driver_attach+0x44/0x5f [<c11833f4>] ? bus_for_each_dev+0x50/0x5a [<c118433e>] ? driver_attach+0x14/0x16 [<c11847f3>] ? __device_attach+0x28/0x28 [<c1184045>] ? bus_add_driver+0xd6/0x1bf [<c1184c22>] ? driver_register+0x78/0xcf [<f8ba8000>] ? 0xf8ba7fff [<c10003bf>] ? do_one_initcall+0x8b/0x121 [<c101e668>] ? change_page_attr_clear+0x2e/0x33 [<f8ba8000>] ? 0xf8ba7fff [<c101e689>] ? set_memory_ro+0x1c/0x20 [<c104de94>] ? set_page_attributes+0x11/0x12 [<c104f6e1>] ? load_module+0x12fa/0x17e8 [<c107483b>] ? map_vm_area+0x22/0x31 [<c104fc36>] ? SyS_init_module+0x67/0x7d [<c1234245>] ? sysenter_do_call+0x12/0x26 Reported-by:
Meelis Roos <mroos@linux.ee> Tested-by:
Meelis Roos <mroos@linux.ee> Signed-off-by:
Sergey Senozhatsky <sergey.senozhatsky@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
This sets up the short audio descriptors properly on DCE3.2 asics for hdmi audio. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The table has the following format: typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure { UCHAR ucNumberOfSrc; USHORT usSrcObjectID[1]; UCHAR ucNumberOfDst; USHORT usDstObjectID[1]; }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; usSrcObjectID[] and usDstObjectID[] are variably sized, so we can't access them directly. Use pointers and update the offset appropriately when accessing the Dst members. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on some boards on resume. The systems seem to work fine without touching this bit so leave it as is. v2: read-modify-write the GART_INDEX_REG_EN bit. I suspect the problem is that we are losing the other settings in the register. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=52952Reported-by:
Ondrej Zary <linux@rainbow-software.org> Tested-by:
Daniel Tobias <dan.g.tob@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
This adds the pci ids for the berlin GPU core. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
This fills in the GPU specific details for berlin GPU cores so that the driver will work with them. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
These blocks need to be ungated for the other parts of the driver properly initialize them (e.g., after a gpu reset, etc.). Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Track the current uvd gated state on CI to avoid unnecessary state changes when uvd is active. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
UVD dpm dynamically adjusts the uvd clocks on demand. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Since we aren't using it when the crtc is disabled, turn it off to save power. The GRPH block is the part of the display controller that controls the primary graphics plane (size, address, etc.). Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These fixes make writes work properly. Previously only reads worked. Note that this feature is off by default. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
If the LCD table contains an EDID record, properly account for the edid size when walking through the records. This should fix error messages about unknown LCD records. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Check the overrides in the firmware info table before enabling spread spectrum on the engine or memory clocks. Some boards may have valid spread spectrum tables, but shouldn't necessarily have it enabled. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce8 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce6 asics. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64850 Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce4.1/5 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Tom Stellard authored
Also add a new RADEON_INFO query to check that CP DMA packets are supported on the compute ring. CP DMA has been supported since the 3.8 kernel, but due to an oversight we forgot to teach the CS checker that the CP DMA packet was legal for the compute ring on Southern Islands GPUs. This patch fixes a bug where the radeon driver will incorrectly reject a legal CP DMA packet from user space. I would like to have the patch backported to stable so that we don't have to require Mesa users to use a bleeding edge kernel in order to take advantage of this feature which is already present in the stable kernels (3.8 and newer). v2: - Don't bump kms version, so this patch can be backported to stable kernels. Cc: stable@vger.kernel.org Signed-off-by:
Tom Stellard <thomas.stellard@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Now that the CP is no longer reset and cg is properly disabled in when appropriate in the dpm code we can now enable mgcg (medium grained clockgating). Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Clockgating needs to be disabled around certain parts of dpm setup otherwise the smc gets into a bad state and dpm doesn't work properly. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Clockgating needs to be disabled around certain parts of dpm setup otherwise the smc gets into a bad state and dpm doesn't work properly. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The format of the clearstate buffer used for pg (powergating) changed between NI and SI. This formats it properly for what the hardware expects on SI+. v2: fix addresses Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Clockgating requires signalling between the CP and the RLC to work properly. Resetting the CP block in the CP resume code messed up the internal coordination between the blocks. Removing the reset allows gfx clockgating to work properly. However, when gfx clock gating is enabled, there is a strange interaction with dpm which causes the chip to stay in the high performance level all the time, so leave gfx clockgating disabled for now. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
- use new cg/pg flags for finer grained clock and powergating control - restructure the cg/pg code so it can be called from other components such as dpm v2: fix build breakage from rebase Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Enable DMA powergating by default. The DMA engines will be powergated when not in use. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The format of the clearstate buffer used for pg (powergating) changed between NI and SI. This formats it properly for what the hardware expects on SI. v2: fix addresses Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Now that the CP is no longer reset and cg is properly disabled in when appropriate in the dpm code we can now enable mgcg (medium grained clockgating). Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Clockgating needs to be disabled around certain parts of dpm setup otherwise the smc gets into a bad state and dpm doesn't work properly. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Clockgating requires signalling between the CP and the RLC to work properly. Resetting the CP block in the CP resume code messed up the internal coordination between the blocks. Removing the reset allows gfx clockgating to work properly. However, when gfx clock gating is enabled, there is a strange interaction with dpm which causes the chip to stay in the high performance level all the time, so leave gfx clockgating disabled for now. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Resturcture clockgating code so that it can be enabled/disabled from other components such as dpm. v2: make function static v3: add fine grained cg controls Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Allows us finer grained control over clock and powergating on SI. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This commits adds flags for supported clockgating and powergating features. This allows us to more easily track which features are supported on a particular asic and to enable/disable features for debugging. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This updates the audio driver to the speaker allocation block from the EDID. A similar change was just implemented for DCE4-8. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This updates the audio driver to the speaker allocation block from the EDID. A similar change was just implemented for DCE6/8. v2: remove unused variables Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Rafał Miłecki <zajec5@gmail.com>
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Rafał Miłecki authored
Do it before enabling audio channels (in AFMT_AUDIO_PACKET_CONTROL2 register). Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Similar to DCE4/5, but supports multiple audio pins which can be assigned per afmt block. v2: rework the driver to handle more than one audio pin. v3: try different dto reg v4: properly program dto v5 (ck): change dto programming order v6: program speaker allocation block v7: rebase v8: rebase on Rafał's changes v9: integrated Rafał's comments, update to latest drm_edid_to_speaker_allocation API v10: add missing line break in error message v11: add back audio enabled messages v12: fix copy paste typo in r600_audio_enable Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Rafał Miłecki <zajec5@gmail.com>
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Rafał Miłecki authored
Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds a helper function to extract the speaker allocation data block from the EDID. This data block describes what speakers are present on the display device. v2: update per Ville Syrjälä's comments v3: fix copy/paste typo in memory allocation Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by:
Rafał Miłecki <zajec5@gmail.com>
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Christian König authored
Similar to separating the UVD code, just put the DMA functions into separate files. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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