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  1. 13 Jun, 2020 1 commit
    • Masahiro Yamada's avatar
      treewide: replace '---help---' in Kconfig files with 'help' · a7f7f624
      Masahiro Yamada authored
      Since commit 84af7a61 ("checkpatch: kconfig: prefer 'help' over
      '---help---'"), the number of '---help---' has been gradually
      decreasing, but there are still more than 2400 instances.
      
      This commit finishes the conversion. While I touched the lines,
      I also fixed the indentation.
      
      There are a variety of indentation styles found.
      
        a) 4 spaces + '---help---'
        b) 7 spaces + '---help---'
        c) 8 spaces + '---help---'
        d) 1 space + 1 tab + '---help---'
        e) 1 tab + '---help---'    (correct indentation)
        f) 1 tab + 1 space + '---help---'
        g) 1 tab + 2 spaces + '---help---'
      
      In order to convert all of them to 1 tab + 'help', I ran the
      following commend:
      
        $ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/'
      Signed-off-by: default avatarMasahiro Yamada <masahiroy@kernel.org>
      a7f7f624
  2. 23 Apr, 2020 1 commit
  3. 17 Apr, 2020 1 commit
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  5. 02 Mar, 2020 1 commit
  6. 25 Feb, 2020 2 commits
  7. 24 Jan, 2020 2 commits
  8. 15 Jan, 2020 1 commit
  9. 22 Nov, 2019 1 commit
  10. 14 Nov, 2019 1 commit
    • Green Wan's avatar
      dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 · 6973886a
      Green Wan authored
      Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed
      Rev A00 board.
      
       - Implement dmaengine APIs, support MEM_TO_MEM async copy.
       - Tested by DMA Test client
       - Supports 4 channels DMA, each channel has 1 done and 1 err
         interrupt connected to platform-level interrupt controller (PLIC).
       - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS
      
      The datasheet is here:
      
        https://static.dev.sifive.com/FU540-C000-v1.0.pdf
      
      Follow the DMAengine controller doc,
      "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA
      engine. And use the dma test client in doc,
      "./Documentation/driver-api/dmaengine/dmatest.rst", to test.
      
      Each DMA channel has separate HW regs and support done and error ISRs.
      4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator
      in DMA HW.
      
         ------               ------
         |    |--< done 23 >--|ch 0|
         |    |--< err  24 >--|    |     (dma0chan0)
         |    |               ------
         |    |               ------
         |    |--< done 25 >--|ch 1|
         |    |--< err  26 >--|    |     (dma0chan1)
         |PLIC|               ------
         |    |               ------
         |    |--< done 27 >--|ch 2|
         |    |--< err  28 >--|    |     (dma0chan2)
         |    |               ------
         |    |               ------
         |    |--< done 29 >--|ch 3|
         |    |--< err  30 >--|    |     (dma0chan3)
         ------               ------
      Signed-off-by: default avatarGreen Wan <green.wan@sifive.com>
      Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
      6973886a
  11. 06 Nov, 2019 1 commit
  12. 18 Oct, 2019 2 commits
  13. 17 Oct, 2019 1 commit
    • Peng Ma's avatar
      dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs · 7fdf9b05
      Peng Ma authored
      DPPA2(Data Path Acceleration Architecture 2) qDMA supports
      virtualized channel by allowing DMA jobs to be enqueued into
      different work queues. Core can initiate a DMA transaction by
      preparing a frame descriptor(FD) for each DMA job and enqueuing
      this job through a hardware portal. DPAA2 components can also
      prepare a FD and enqueue a DMA job through a hardware portal.
      The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
      then schedules and dispatches to internal DMA hardware engines,
      which generate read and write requests. Both qDMA source data and
      destination data can be either contiguous or non-contiguous using
      one or more scatter/gather tables.
      The qDMA supports global bandwidth flow control where all DMA
      transactions are stalled if the bandwidth threshold has been reached.
      Also supported are transaction based read throttling.
      
      Add NXP dppa2 qDMA to support some of Layerscape SoCs.
      such as: LS1088A, LS208xA, LX2, etc.
      Signed-off-by: default avatarPeng Ma <peng.ma@nxp.com>
      Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
      7fdf9b05
  14. 14 Aug, 2019 2 commits
  15. 30 Jul, 2019 1 commit
  16. 05 Jul, 2019 1 commit
  17. 14 Jun, 2019 1 commit
  18. 10 Jun, 2019 1 commit
    • Gustavo Pimentel's avatar
      dmaengine: Add Synopsys eDMA IP core driver · e63d79d1
      Gustavo Pimentel authored
      Add Synopsys PCIe Endpoint eDMA IP core driver to kernel.
      
      This IP is generally distributed with Synopsys PCIe Endpoint IP (depends
      of the use and licensing agreement).
      
      This core driver, initializes and configures the eDMA IP using vma-helpers
      functions and dma-engine subsystem.
      
      This driver can be compile as built-in or external module in kernel.
      
      To enable this driver just select DW_EDMA option in kernel configuration,
      however it requires and selects automatically DMA_ENGINE and
      DMA_VIRTUAL_CHANNELS option too.
      
      In order to transfer data from point A to B as fast as possible this IP
      requires a dedicated memory space containing linked list of elements.
      
      All elements of this linked list are continuous and each one describes a
      data transfer (source and destination addresses, length and a control
      variable).
      
      For the sake of simplicity, lets assume a memory space for channel write
      0 which allows about 42 elements.
      
      +---------+
      | Desc #0 |-+
      +---------+ |
                  V
             +----------+
             | Chunk #0 |-+
             |  CB = 1  | |  +----------+  +-----+  +-----------+  +-----+
             +----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp |
                  |          +----------+  +-----+  +-----------+  +-----+
                  V
             +----------+
             | Chunk #1 |-+
             |  CB = 0  | |  +-----------+  +-----+  +-----------+  +-----+
             +----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp |
                  |          +-----------+  +-----+  +-----------+  +-----+
                  V
             +----------+
             | Chunk #2 |-+
             |  CB = 1  | |  +-----------+  +-----+  +------------+  +-----+
             +----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp |
                  |          +-----------+  +-----+  +------------+  +-----+
                  V
             +----------+
             | Chunk #3 |-+
             |  CB = 0  | |  +------------+  +-----+  +------------+  +-----+
             +----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp |
                             +------------+  +-----+  +------------+  +-----+
      
      Legend:
       - Linked list, also know as Chunk
       - Linked list element*, also know as Burst *CB*, also know as Change Bit,
      it's a control bit (and typically is toggled) that allows to easily
      identify and differentiate between the current linked list and the
      previous or the next one.
       - LLP, is a special element that indicates the end of the linked list
      element stream also informs that the next CB should be toggle
      
      On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or
      even Burst #129) is set some flags on their control variable (RIE and
      LIE bits) that will trigger the send of "done" interruption.
      
      On the interruptions callback, is decided whether to recycle the linked
      list memory space by writing a new set of Bursts elements (if still
      exists Chunks to transfer) or is considered completed (if there is no
      Chunks available to transfer).
      
      On scatter-gather transfer mode, the client will submit a scatter-gather
      list of n (on this case 130) elements, that will be divide in multiple
      Chunks, each Chunk will have (on this case 42) a limited number of
      Bursts and after transferring all Bursts, an interrupt will be
      triggered, which will allow to recycle the all linked list dedicated
      memory again with the new information relative to the next Chunk and
      respective Burst associated and repeat the whole cycle again.
      
      On cyclic transfer mode, the client will submit a buffer pointer, length
      of it and number of repetitions, in this case each burst will correspond
      directly to each repetition.
      
      Each Burst can describes a data transfer from point A(source) to point
      B(destination) with a length that can be from 1 byte up to 4 GB. Since
      dedicated the memory space where the linked list will reside is limited,
      the whole n burst elements will be organized in several Chunks, that
      will be used later to recycle the dedicated memory space to initiate a
      new sequence of data transfers.
      
      The whole transfer is considered has completed when it was transferred
      all bursts.
      
      Currently this IP has a set well-known register map, which includes
      support for legacy and unroll modes. Legacy mode is version of this
      register map that has multiplexer register that allows to switch
      registers between all write and read channels and the unroll modes
      repeats all write and read channels registers with an offset between
      them. This register map is called v0.
      
      The IP team is creating a new register map more suitable to the latest
      PCIe features, that very likely will change the map register, which this
      version will be called v1. As soon as this new version is released by
      the IP team the support for this version in be included on this driver.
      
      According to the logic, patches 1, 2 and 3 should be squashed into 1
      unique patch, but for the sake of simplicity of review, it was divided
      in this 3 patches files.
      Signed-off-by: default avatarGustavo Pimentel <gustavo.pimentel@synopsys.com>
      Cc: Vinod Koul <vkoul@kernel.org>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Russell King <rmk+kernel@armlinux.org.uk>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
      e63d79d1
  19. 21 May, 2019 1 commit
  20. 25 Mar, 2019 1 commit
  21. 07 Jan, 2019 1 commit
  22. 24 Nov, 2018 1 commit
  23. 11 Sep, 2018 3 commits
  24. 29 Aug, 2018 1 commit
  25. 09 Aug, 2018 1 commit
  26. 25 Jul, 2018 1 commit
  27. 20 Jul, 2018 1 commit
  28. 02 Jul, 2018 1 commit
    • Robin Gong's avatar
      dmaengine: imx-sdma: add virt-dma support · 57b772b8
      Robin Gong authored
      The legacy sdma driver has below limitations or drawbacks:
        1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc
           one page size for one channel regardless of only few BDs needed
           most time. But in few cases, the max PAGE_SIZE maybe not enough.
        2. One SDMA channel can't stop immediatley once channel disabled which
           means SDMA interrupt may come in after this channel terminated.There
           are some patches for this corner case such as commit "2746e2c3",
           but not cover non-cyclic.
      
      The common virt-dma overcomes the above limitations. It can alloc bd
      dynamically and free bd once this tx transfer done. No memory wasted or
      maximum limititation here, only depends on how many memory can be requested
      from kernel. For No.2, such issue can be workaround by checking if there
      is available descript("sdmac->desc") now once the unwanted interrupt
      coming. At last the common virt-dma is easier for sdma driver maintain.
      Signed-off-by: default avatarRobin Gong <yibin.gong@nxp.com>
      Reviewed-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
      Tested-by: default avatarLucas Stach <l.stach@pengutronix.de>
      Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
      57b772b8
  29. 25 Apr, 2018 1 commit
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  34. 12 Oct, 2017 1 commit