An error occurred fetching the project authors.
- 13 Jun, 2020 1 commit
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Masahiro Yamada authored
Since commit 84af7a61 ("checkpatch: kconfig: prefer 'help' over '---help---'"), the number of '---help---' has been gradually decreasing, but there are still more than 2400 instances. This commit finishes the conversion. While I touched the lines, I also fixed the indentation. There are a variety of indentation styles found. a) 4 spaces + '---help---' b) 7 spaces + '---help---' c) 8 spaces + '---help---' d) 1 space + 1 tab + '---help---' e) 1 tab + '---help---' (correct indentation) f) 1 tab + 1 space + '---help---' g) 1 tab + 2 spaces + '---help---' In order to convert all of them to 1 tab + 'help', I ran the following commend: $ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/' Signed-off-by:
Masahiro Yamada <masahiroy@kernel.org>
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- 23 Apr, 2020 1 commit
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Lubomir Rintel authored
A generic SRAM will driver for Device Tree enabled platforms will do as well. The non-DT drivers that use mmp_tdma to transfer audio samples to and from the audio SRAM should depend on MMP_SRAM themselves. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200419164912.670973-8-lkundrak@v3.skSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 17 Apr, 2020 1 commit
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Geert Uytterhoeven authored
According to https://www.analog.com/, the company name is spelled "Analog Devices". Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20200416103058.15269-3-geert+renesas@glider.be [vkoul: make subsystem name dmaengine] Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 15 Apr, 2020 1 commit
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YueHaibing authored
If PCI_MSI is not set, building fais: drivers/dma/hisi_dma.c: In function ‘hisi_dma_free_irq_vectors’: drivers/dma/hisi_dma.c:138:2: error: implicit declaration of function ‘pci_free_irq_vectors’; did you mean ‘pci_alloc_irq_vectors’? [-Werror=implicit-function-declaration] pci_free_irq_vectors(data); ^~~~~~~~~~~~~~~~~~~~ Make HISI_DMA depends on PCI_MSI to fix this. Fixes: e9f08b65 ("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200328114133.17560-1-yuehaibing@huawei.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 02 Mar, 2020 1 commit
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Kunihiko Hayashi authored
This adds external DMA controller driver implemented in Socionext UniPhier SoCs. This driver supports DMA_MEMCPY and DMA_SLAVE modes. Since this driver does not support the the way to transfer size unaligned to burst width, 'src_maxburst' or 'dst_maxburst' of dma_slave_config must be 1 to transfer arbitrary size. If transfer size is unaligned to burst size, the transfer isn't started and the driver displays an error message. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1582271550-3403-3-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 25 Feb, 2020 2 commits
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Dmitry Osipenko authored
There is nothing arch-specific in the driver's code, so let's enable compile-testing for the driver. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20200209163356.6439-18-digetx@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Dmitry Osipenko authored
The driver's removal was fixed by a recent commit and module load/unload is working well now, tested on Tegra30. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20200209163356.6439-16-digetx@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 24 Jan, 2020 2 commits
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Zhou Wang authored
This patch adds a driver for HiSilicon Kunpeng DMA engine. This DMA engine which is an PCIe iEP offers 30 channels, each channel has a send queue, a complete queue and an interrupt to help to do tasks. This DMA engine can do memory copy between memory blocks or between memory and device buffer. Signed-off-by:
Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by:
Zhenfa Qiu <qiuzhenfa@hisilicon.com> Link: https://lore.kernel.org/r/1579155057-80523-1-git-send-email-wangzhou1@hisilicon.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
The idxd driver introduces the Intel Data Stream Accelerator [1] that will be available on future Intel Xeon CPUs. One of the kernel access point for the driver is through the dmaengine subsystem. It will initially provide the DMA copy service to the kernel. Some of the main functionality introduced with this accelerator are: shared virtual memory (SVM) support, and descriptor submission using Intel CPU instructions movdir64b and enqcmds. There will be additional accelerator devices that share the same driver with variations to capabilities. This commit introduces the probe and initialization component of the driver. [1]: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specificationSigned-off-by:
Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/157965023991.73301.6186843973135311580.stgit@djiang5-desk3.ch.intel.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 15 Jan, 2020 1 commit
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Logan Gunthorpe authored
Some PLX Switches can expose DMA engines via extra PCI functions on the upstream port. Each function will have one DMA channel. This patch is just the core PCI driver skeleton and dma engine registration. Signed-off-by:
Logan Gunthorpe <logang@deltatee.com> Link: https://lore.kernel.org/r/20200103212021.2881-2-logang@deltatee.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 22 Nov, 2019 1 commit
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Krzysztof Kozlowski authored
Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1574306348-29212-1-git-send-email-krzk@kernel.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 14 Nov, 2019 1 commit
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Green Wan authored
Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed Rev A00 board. - Implement dmaengine APIs, support MEM_TO_MEM async copy. - Tested by DMA Test client - Supports 4 channels DMA, each channel has 1 done and 1 err interrupt connected to platform-level interrupt controller (PLIC). - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS The datasheet is here: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Follow the DMAengine controller doc, "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA engine. And use the dma test client in doc, "./Documentation/driver-api/dmaengine/dmatest.rst", to test. Each DMA channel has separate HW regs and support done and error ISRs. 4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator in DMA HW. ------ ------ | |--< done 23 >--|ch 0| | |--< err 24 >--| | (dma0chan0) | | ------ | | ------ | |--< done 25 >--|ch 1| | |--< err 26 >--| | (dma0chan1) |PLIC| ------ | | ------ | |--< done 27 >--|ch 2| | |--< err 28 >--| | (dma0chan2) | | ------ | | ------ | |--< done 29 >--|ch 3| | |--< err 30 >--| | (dma0chan3) ------ ------ Signed-off-by:
Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 06 Nov, 2019 1 commit
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Radhey Shyam Pandey authored
Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by:
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 18 Oct, 2019 2 commits
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Jassi Brar authored
Driver for Socionext Milbeaut XDMAC controller. The controller only supports Mem-To-Mem transfers over upto 8 configurable channels. Signed-off-by:
Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033219.14713-1-jassisinghbrar@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Jassi Brar authored
Driver for Socionext Milbeaut HDMAC controller. The controller has upto 8 floating channels, that need a predefined slave-id to work from a set of slaves. Signed-off-by:
Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033359.14925-1-jassisinghbrar@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 17 Oct, 2019 1 commit
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Peng Ma authored
DPPA2(Data Path Acceleration Architecture 2) qDMA supports virtualized channel by allowing DMA jobs to be enqueued into different work queues. Core can initiate a DMA transaction by preparing a frame descriptor(FD) for each DMA job and enqueuing this job through a hardware portal. DPAA2 components can also prepare a FD and enqueue a DMA job through a hardware portal. The qDMA prefetches DMA jobs through DPAA2 hardware portal. It then schedules and dispatches to internal DMA hardware engines, which generate read and write requests. Both qDMA source data and destination data can be either contiguous or non-contiguous using one or more scatter/gather tables. The qDMA supports global bandwidth flow control where all DMA transactions are stalled if the bandwidth threshold has been reached. Also supported are transaction based read throttling. Add NXP dppa2 qDMA to support some of Layerscape SoCs. such as: LS1088A, LS208xA, LX2, etc. Signed-off-by:
Peng Ma <peng.ma@nxp.com> Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 14 Aug, 2019 2 commits
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Arnd Bergmann authored
Now that iop3xx and iop13xx are gone, the iop-adma driver no longer needs to deal with incompatible register layout defined in machine specific header files. Move the iop32x specific definitions into drivers/dma/iop-adma.h and the platform_data into include/linux/platform_data/dma-iop32x.h, and change the machine code to no longer reference those. The DMA0_ID/DMA1_ID/AAU_ID macros are required as part of the platform data interface and still need to be visible, so move those from one header to the other. Link: https://lore.kernel.org/r/20190809163334.489360-4-arnd@arndb.deSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
There are three families of IOP machines we support in Linux: iop32x (which includes EP80219), iop33x and iop13xx (aka IOP34x aka WP8134x). All products we support in the kernel are based on the first of these, iop32x, the other families only ever supported the Intel reference boards but no actual machine anyone could ever buy. While one could clearly make them all three work in a single kernel with some work, this takes the easy way out, removing the later two platforms entirely, under the assumption that there are no remaining users. Earlier versions of OpenWRT and Debian both had support for iop32x but not the others, and they both dropped iop32x as well in their 2015 releases. Link: https://lore.kernel.org/r/20190809163334.489360-1-arnd@arndb.deSigned-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by: Wolfram Sang <wsa@the-dreams.de> # for I2C parts Acked-by:
Dan Williams <dan.j.williams@intel.com> Acked-by:
Martin Michlmayr <tbm@cyrius.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 30 Jul, 2019 1 commit
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Paul Cercueil authored
The newer and better JZ4780 driver is now used to provide DMA functionality on the JZ4740. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Tested-by:
Artur Rojek <contact@artur-rojek.eu> Acked-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
Paul Burton <paul.burton@mips.com>
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- 05 Jul, 2019 1 commit
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Sameer Pujar authored
Tegra ADMA does not use pm-clk interface now and hence the dependency is removed from Kconfig. Signed-off-by:
Sameer Pujar <spujar@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 14 Jun, 2019 1 commit
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Alexandru Ardelean authored
The registers for AXI DMAC are detailed at: https://wiki.analog.com/resources/fpga/docs/axi_dmac#register_map This change adds regmap support for these registers, in case some wants to have a more direct access to them via this interface. Signed-off-by:
Alexandru Ardelean <alexandru.ardelean@analog.com> [vkoul: fixed code style issue] Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 10 Jun, 2019 1 commit
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Gustavo Pimentel authored
Add Synopsys PCIe Endpoint eDMA IP core driver to kernel. This IP is generally distributed with Synopsys PCIe Endpoint IP (depends of the use and licensing agreement). This core driver, initializes and configures the eDMA IP using vma-helpers functions and dma-engine subsystem. This driver can be compile as built-in or external module in kernel. To enable this driver just select DW_EDMA option in kernel configuration, however it requires and selects automatically DMA_ENGINE and DMA_VIRTUAL_CHANNELS option too. In order to transfer data from point A to B as fast as possible this IP requires a dedicated memory space containing linked list of elements. All elements of this linked list are continuous and each one describes a data transfer (source and destination addresses, length and a control variable). For the sake of simplicity, lets assume a memory space for channel write 0 which allows about 42 elements. +---------+ | Desc #0 |-+ +---------+ | V +----------+ | Chunk #0 |-+ | CB = 1 | | +----------+ +-----+ +-----------+ +-----+ +----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp | | +----------+ +-----+ +-----------+ +-----+ V +----------+ | Chunk #1 |-+ | CB = 0 | | +-----------+ +-----+ +-----------+ +-----+ +----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp | | +-----------+ +-----+ +-----------+ +-----+ V +----------+ | Chunk #2 |-+ | CB = 1 | | +-----------+ +-----+ +------------+ +-----+ +----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp | | +-----------+ +-----+ +------------+ +-----+ V +----------+ | Chunk #3 |-+ | CB = 0 | | +------------+ +-----+ +------------+ +-----+ +----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp | +------------+ +-----+ +------------+ +-----+ Legend: - Linked list, also know as Chunk - Linked list element*, also know as Burst *CB*, also know as Change Bit, it's a control bit (and typically is toggled) that allows to easily identify and differentiate between the current linked list and the previous or the next one. - LLP, is a special element that indicates the end of the linked list element stream also informs that the next CB should be toggle On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or even Burst #129) is set some flags on their control variable (RIE and LIE bits) that will trigger the send of "done" interruption. On the interruptions callback, is decided whether to recycle the linked list memory space by writing a new set of Bursts elements (if still exists Chunks to transfer) or is considered completed (if there is no Chunks available to transfer). On scatter-gather transfer mode, the client will submit a scatter-gather list of n (on this case 130) elements, that will be divide in multiple Chunks, each Chunk will have (on this case 42) a limited number of Bursts and after transferring all Bursts, an interrupt will be triggered, which will allow to recycle the all linked list dedicated memory again with the new information relative to the next Chunk and respective Burst associated and repeat the whole cycle again. On cyclic transfer mode, the client will submit a buffer pointer, length of it and number of repetitions, in this case each burst will correspond directly to each repetition. Each Burst can describes a data transfer from point A(source) to point B(destination) with a length that can be from 1 byte up to 4 GB. Since dedicated the memory space where the linked list will reside is limited, the whole n burst elements will be organized in several Chunks, that will be used later to recycle the dedicated memory space to initiate a new sequence of data transfers. The whole transfer is considered has completed when it was transferred all bursts. Currently this IP has a set well-known register map, which includes support for legacy and unroll modes. Legacy mode is version of this register map that has multiplexer register that allows to switch registers between all write and read channels and the unroll modes repeats all write and read channels registers with an offset between them. This register map is called v0. The IP team is creating a new register map more suitable to the latest PCIe features, that very likely will change the map register, which this version will be called v1. As soon as this new version is released by the IP team the support for this version in be included on this driver. According to the logic, patches 1, 2 and 3 should be squashed into 1 unique patch, but for the sake of simplicity of review, it was divided in this 3 patches files. Signed-off-by:
Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Joao Pinto <jpinto@synopsys.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 21 May, 2019 1 commit
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Thomas Gleixner authored
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 25 Mar, 2019 1 commit
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Michael Hennerich authored
The AXI DMAC driver is currently supported also on the Xilinx ZynqMP architecture. This change allows this driver to be enabled & used on it as well. Signed-off-by:
Michael Hennerich <michael.hennerich@analog.com> Signed-off-by:
Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 07 Jan, 2019 1 commit
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Peng Ma authored
NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel virtuallization by allowing DMA jobs to be enqueued into different command queues. Signed-off-by:
Wen He <wen.he_1@nxp.com> Signed-off-by:
Jiaheng Fan <jiaheng.fan@nxp.com> Signed-off-by:
Peng Ma <peng.ma@nxp.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 24 Nov, 2018 1 commit
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Masahiro Yamada authored
The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4, Pro4, and sLD8 SoCs. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 11 Sep, 2018 3 commits
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Paul Cercueil authored
If we make this driver depend on MACH_JZ4780, that means it can be enabled only if we're building a kernel specially crafted for a JZ4780-based board, while most GNU/Linux distributions will want one generic MIPS kernel that works on multiple boards. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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Angelo Dureghello authored
This patch adds support for ColdFire mcf5441x-family edma module. The ColdFire edma module is slightly different from fsl-edma, so a new driver is added. But most of the code is common between fsl-edma and mcf-edma so it has been collected into a separate common module fsl-edma-common (patch 1/3). Signed-off-by:
Angelo Dureghello <angelo@sysam.it> Tested-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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Vinod Koul authored
We have build failures attributed to turning on COMPILE_TEST, so revert commit 90082cd3: ("dmaengine: add COMPILE_TEST for the drivers") while we fix these. Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 29 Aug, 2018 1 commit
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Huang Shijie authored
We can do the compiling test with COMPILE_TEST. This patch adds the COMPILE_TEST for the drivers. Signed-off-by:
Huang Shijie <sjhuang@iluvatar.ai> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 09 Aug, 2018 1 commit
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Manivannan Sadhasivam authored
Add Actions Semi Owl family S900 DMA driver. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 25 Jul, 2018 1 commit
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Vinod Koul authored
This reverts commit 31d5e6b7: ("dmaengine: mv_xor_v2: enable COMPILE_TEST") as enabling causing bunch of build failures. Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 20 Jul, 2018 1 commit
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Hanna Hawa authored
To get more coverage, enable COMPILE_TEST for this driver. Signed-off-by:
Hanna Hawa <hannah@marvell.com> Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 02 Jul, 2018 1 commit
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Robin Gong authored
The legacy sdma driver has below limitations or drawbacks: 1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc one page size for one channel regardless of only few BDs needed most time. But in few cases, the max PAGE_SIZE maybe not enough. 2. One SDMA channel can't stop immediatley once channel disabled which means SDMA interrupt may come in after this channel terminated.There are some patches for this corner case such as commit "2746e2c3", but not cover non-cyclic. The common virt-dma overcomes the above limitations. It can alloc bd dynamically and free bd once this tx transfer done. No memory wasted or maximum limititation here, only depends on how many memory can be requested from kernel. For No.2, such issue can be workaround by checking if there is available descript("sdmac->desc") now once the unwanted interrupt coming. At last the common virt-dma is easier for sdma driver maintain. Signed-off-by:
Robin Gong <yibin.gong@nxp.com> Reviewed-by:
Sascha Hauer <s.hauer@pengutronix.de> Tested-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 25 Apr, 2018 1 commit
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Peter Ujfalusi authored
Collect the Texas Instruments DMA drivers under drivers/dma/ti/ Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 27 Mar, 2018 1 commit
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Sean Wang authored
MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has a single ring is dedicated to memory-to-memory transfer through ring based descriptor management. Even though there is only one physical ring available inside HSDMA, the driver can be easily extended to the support of multiple virtual channels processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort. Signed-off-by:
Sean Wang <sean.wang@mediatek.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 19 Mar, 2018 1 commit
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Eugeniy Paltsev authored
This patch adds support for the DW AXI DMAC controller. DW AXI DMAC is a part of HSDK development board from Synopsys. In this driver implementation only DMA_MEMCPY transfers are supported. Signed-off-by:
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 24 Oct, 2017 1 commit
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Baolin Wang authored
This patch adds the DMA controller driver for Spreadtrum SC9860 platform. Signed-off-by:
Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 23 Oct, 2017 1 commit
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Anup Patel authored
By default, we build Broadcom SBA RAID driver as loadable module for iProc SOCs so that kernel image is little smaller and we load SBA RAID driver only when required. Signed-off-by:
Anup Patel <anup.patel@broadcom.com> Reviewed-by:
Scott Branden <scott.branden@broadcom.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 12 Oct, 2017 1 commit
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Arnd Bergmann authored
Without CONFIG_OF we get a build warning: warning: (STM32_MDMA) selects DMA_OF which has unmet direct dependencies (DMADEVICES && OF) This adds a dependency on CONFIG_OF. Since this means we no longer need to select 'DMA_OF', I'm dropping that line as well. Fixes: a4ffb13c ("dmaengine: Add STM32 MDMA driver") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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