- 23 Sep, 2021 13 commits
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Joshua Ashton authored
Adds the missing logic to set the correct value of dcc_ind_blk for this tiling version. Signed-off-by:
Joshua Ashton <joshua@froggi.es> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Joshua Ashton authored
We don't need to do this workaround if we start setting this value when we fill the plane attributes. Acked-by:
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Colin Ian King authored
Don't populate the read-only array encoded_lanes on the stack but instead it static. Also makes the object code smaller by 97 bytes: Before: text data bss dec hex filename 38899 8064 0 46963 b773 ./drivers/gpu/drm/radeon/r600_dpm.o After: text data bss dec hex filename 38738 8128 0 46866 b712 ./drivers/gpu/drm/radeon/r600_dpm.o (gcc version 11.2.0) Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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John Clements authored
Set correct RAS nBIF error query register offsets on aldebaran Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Candice Li authored
Update PSP TA unload function to use PSP TA context as input argument. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Candice Li authored
Update asd_context structure and add asd_initialize function to conform ASD header/loading to generic TA systems. Signed-off-by:
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Alex Deucher authored
Was missing. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The "base_addr_is_mc_addr" field was added for dcn3.1 support but pa_config was never updated to set it to false. Uninitialized memory causes it to be set to true which results in address mistranslation and white screen. [How] Use memset to ensure all fields are initialized to 0 by default. Fixes: 64b1d0e8 ("drm/amd/display: Add DCN3.1 HWSEQ") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Simon Ser authored
This patch allows panel orientation quirks from DRM core to be used. They attach a DRM connector property "panel orientation" which indicates in which direction the panel has been mounted. Some machines have the internal screen mounted with a rotation. Since the panel orientation quirks need the native mode from the EDID, check for it in amdgpu_dm_connector_ddc_get_modes. Signed-off-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Paul Menzel authored
As the user cannot do anything about the unsupported Trusted Memory Zone (TMZ) feature, do not warn about it, but make it informational, so demote the log level from warning to info. Signed-off-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
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Michel Dänzer authored
This was unusual; normally, inline functions are declared static as well, and defined in a header file if used by multiple compilation units. The latter would be more involved in this case, so just drop the inline declaration for now. Fixes compile failure building for ppc64le on RHEL 8: In file included from ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h:32, from ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:33: ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_recovery_init’: ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:90:17: error: inlining failed in call to ‘always_inline’ ‘amdgpu_ras_eeprom_max_record_count’: function body not available 90 | inline uint32_t amdgpu_ras_eeprom_max_record_count(void); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1985:34: note: called from here 1985 | max_eeprom_records_len = amdgpu_ras_eeprom_max_record_count(); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: c84d4670 "drm/amdgpu: validate bad page threshold in ras(v3)" Reviewed-by:Lyude Paul <lyude@redhat.com> Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Nirmoy Das authored
Pass drm dev directly as rdev->ddev gets initialized later on at radeon_device_init(). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214375Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Evan Quan authored
Current RUNPM mechanism relies on PMFW to master the timing for BACO in/exit. And that needs cooperation from sound driver for dstate change notification for function 1(audio). Otherwise(on sound driver missing), BACO cannot be kicked in correctly and hang will be observed on RUNPM exit. By switching back to legacy message way on sound driver missing, we are able to fix the runpm hang observed for the scenario below: amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded Signed-off-by:
Evan Quan <evan.quan@amd.com> Reported-and-tested-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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- 14 Sep, 2021 27 commits
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xinhui pan authored
Direct IB submission should be exclusive. So use write lock. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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xinhui pan authored
alloc extra msg from direct IB pool. Signed-off-by:
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xinhui pan authored
alloc extra msg from direct IB pool. Signed-off-by:
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xinhui pan authored
move BO allocation in sw_init. Signed-off-by:
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Candice Li authored
Remove all TA binary structures and add the specific binary structure in struct ta_context. Signed-off-by:
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James Zhu authored
Separate iommu_resume from kfd_resume, and move it before other amdgpu ip init/resume. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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James Zhu authored
Add amdgpu_amdkfd_resume_iommu for amdgpu. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277Signed-off-by:
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James Zhu authored
Separate kfd_iommu_resume from kfd_resume for fine-tuning of amdgpu device init/resume/reset/recovery sequence. v2: squash in fix for !CONFIG_HSA_AMD Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277Signed-off-by:
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shaoyunl authored
The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies to all associated VFs. so guest driver can not directly enable the atomicOps for VF, it depends on PF to enable it. In current design, amdgpu driver will get the enabled atomicOps bits through private pf2vf data Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Michael Strauss authored
[WHY] Sequences to handle powering down these sub-IP blocks are now ready for use Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Ian Chen authored
Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Power down VPG and AFMT blocks when not in use [HOW] Create afmt31 and vpg31 structs and add necessary fields to reg list Reviewed-by:
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Jaehyun Chung authored
[Why] Degamma coefficients are calculated in our degamma formula using the regamma coefficients. We do not need to add separate degamma coefficients. [How] Remove the change to add separate degamma coefficients. Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Jaehyun Chung <jaehyun.chung@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] If link training is aborted, it shall be retried if sink is present. [How] Check hpd status to find out whether sink is present or not. If sink is present, then link training shall be tried again with same settings. Otherwise, link training shall be aborted. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Qingqing Zhuo authored
[Why] Intermittently, there presents two occurrences of 0 stream commits in a single HPD event. Current HDCP sequence does not consider such scenerio, and will thus disable HDCP. [How] Add condition check to include stream remove and re-enable case for HDCP enable. Reviewed-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Aric Cyr authored
* Correct degamma coefficients * Optimize bandwidth on following fast update * Fix multiple memory leaks reported by coverity * Get backlight from PWM if DMCU is not initialized Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Jaehyun Chung authored
[Why] Some incorrect coefficients were being used Reviewed-by:
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Anthony Koo authored
* PSR SMU optimizations * MST dock fixes Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Yang authored
[Why] When system is in Z10 HPD interrupts cannot fire, we may miss display configuration changes. [How] When Zstate is enabled, if DMUB indicate DCN has lost power, do a complete detection periodically. Reviewed-by:
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Hersen Wu authored
[Why] call stack of amdgpu dsc mst pbn, slot num calculation is as below: -compute_bpp_x16_from_target_bandwidth -decide_dsc_target_bpp_x16 -setup_dsc_config -dc_dsc_compute_bandwidth_range -compute_mst_dsc_configs_for_link -compute_mst_dsc_configs_for_state from pbn -> dsc target bpp_x16 bpp_x16 is calulated by compute_bpp_x16_from_target_bandwidth. Beside pixel clock and bpp, num_slices_h and bpp_increment_div will also affect bpp_x16. from dsc target bpp_x16 -> pbn within dm_update_mst_vcpi_slots_for_dsc, pbn = drm_dp_calc_pbn_mode(clock, bpp_x16, true); drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), 8 * 54 * 1000 * 1000); } bpp / 16 trunc digits after decimal point. This will cause calculation delta. drm_dp_calc_pbn_mode does not have other informations, like num_slices_h, bpp_increment_div. therefore, it does not do revese calcuation properly from bpp_x16 to pbn. pbn from drm_dp_calc_pbn_mode is less than pbn from compute_mst_dsc_configs_for_state. This cause not enough mst slot allocated to display. display could not visually light up. [How] pass pbn from compute_mst_dsc_configs_for_state to dm_update_mst_vcpi_slots_for_dsc Cc: stable@vger.kernel.org Reviewed-by:Scott Foster <Scott.Foster@amd.com> Acked-by:
Hersen Wu <hersenwu@amd.com> Tested-by:
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Dale Zhao authored
[Why] In some scenarios like fullscreen game, major plane is scaled. Then if a upper layer owns the cursor, cursor is invisiable in the majority of the screen. [How] Instead assuming upper plane handles cursor, summing up upper split planes on the same layer. If whole upper plane covers current half/whole pipe plane, disable cursor. Reviewed-by:
Dale Zhao <dale.zhao@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] The current call to optimize_bandwidth never occurs because flip is always pending from the FULL and FAST updates. [How] Optimize on the following flip when it's a FAST update and we know we aren't going to be modifying the clocks again. Reviewed-by:
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Qingqing Zhuo authored
[Why] HPD disable and enable sequences are not mutually exclusive on Linux. For HPDs that spans under 1s (i.e. HPD low = 1s), part of the disable sequence (specifically, a request to SMU to lower refclk) could come right before the call to PHY enablement, causing DMUB to access an irresponsive PHY and thus a hard hang on the system. [How] Disable 48mhz refclk off when there is any HPD status in connected state. Reviewed-by:
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Jaehyun Chung authored
[Why] In YUV case, need to set the input TF to sRGB instead of BT709, even though the input TF type is distributed. SRGB was not being used because pixel format was not being set in the surface update sequence. Also, we were using the same coefficients for degamma and regamma formula, causing the cutoff point of the linear section of the curve to be incorrect. [How] Set pixel format in the surface update sequence. Add separate coefficient arrays for regamma and degamma. Reviewed-by:
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Anson Jacob authored
This reverts commit f5b6a20c. This patch broke new settings from taking effect. Hotplug is required for new settings to take effect. Reviewed-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
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Harry Wentland authored
On Carrizo/Stoney systems we set backlight through panel_cntl, i.e. directly via the PWM registers, if DMCU is not initialized. We always read it back through ABM registers which leads to a mismatch and forces atomic_commit to program the backlight each time. Instead make sure we use the same logic for backlight readback, i.e. read it from panel_cntl if DMCU is not initialized. We also need to remove some extraneous and incorrect calculations at the end of dce_get_16_bit_backlight_from_pwm. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1666 Cc: stable@vger.kernel.org Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
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Anson Jacob authored
coccinelle patch used: @@ expression enc1,vpg,afmt; @@ - if (!enc1 || !vpg || !afmt) + if (!enc1 || !vpg || !afmt) { + kfree(enc1); + kfree(vpg); + kfree(afmt); return NULL; + } Addresses-Coverity-ID: 1466017: ("Resource leaks") Reviewed-by:Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by:
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