- 04 Jun, 2015 40 commits
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Christian König authored
Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com>
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monk.liu authored
sg could point to array of contigiouse page*, only free page could lead to memory leak. v2: use iterator Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jammy Zhou authored
This flag isn't used by user mode drivers, remove it to avoid confusion. And rename GTT_WC to GTT_USWC to make it clear. Signed-off-by:
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Sonny Jiang authored
Fix crash when disabling dpm. v2: agd5f: fix coding style, cleanup commit message Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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Alex Deucher authored
Avoids possibility that info may leak via the uninitialized _pad element. Noticed-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Alex Deucher authored
Need to unlock the mutex on error. Noticed-by:
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monk.liu authored
this could prevent mis-understanding, because libdrm side will consider no bo_list created if handleis zero Signed-off-by:
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monk.liu authored
Still need to handle ibs BO and validate them even bo_list is NULL Signed-off-by:
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Jack Xiao authored
Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Alex Deucher authored
amdgpu_bo_create() calls amdgpu_ttm_placement_from_domain() before ttm_bo_init() is called. amdgpu_ttm_placement_from_domain() uses the ttm bo size to determine when to select top down allocation but since the ttm bo is not initialized yet the check is always false. It only took affect when buffers were validated later. It also seemed to regress suspend and resume on some systems possibly due to it not taking affect in amdgpu_bo_create(). amdgpu_bo_create() and amdgpu_ttm_placement_from_domain() need to be reworked substantially for this to be optimally effective. Re-enable it at that point. Ported from radeon commit: a239118aSigned-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
This adds initial support for VI asics. This includes Iceland, Tonga, and Carrizo. Our inital focus as been Carrizo, so there are still gaps in support for Tonga and Iceland, notably power management. Acked-by:
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Alex Deucher authored
This patch adds support for CIK parts. These parts are also supported by radeon which is the preferred option, so there is a config option to enable support for CIK parts in amdgpu for testing. Acked-by:
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Alex Deucher authored
Use readb() and memcpy_fromio() accessors instead. Ported from radeon commit: f2c9e560Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by:
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Alex Deucher authored
This is the main header file for amdgpu. v2: remove stable comments Acked-by:
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Alex Deucher authored
This header defines asic families and attributes. Acked-by:
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Alex Deucher authored
This header provides the smc message interface for the driver. Acked-by:
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Alex Deucher authored
This header provides for format for the GCA blocks clear state (i.e., default state). Each GCA version has a specific clear state. Acked-by:
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Alex Deucher authored
These headers define the atombios table structure and driver interface. Acked-by:
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Alex Deucher authored
This header defines the ioctl interface to the driver. v2: remove stale tiling defines v3: add appropriate padding v4: remove executable bits on header Acked-by:
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Alex Deucher authored
These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by:
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