- 29 May, 2018 12 commits
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Eric Bernstein authored
Add register programming to support TMZ and DCC on secondary surfaces. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Bernstein authored
Add register programming to support 16bpc component depth for DP. Signed-off-by:
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Roman Li authored
Fixing warning on dce10 with HDMI display. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Mikita Lipski authored
If connector doesn't have a sink, fake sink is created, but never released as it assumed that its destroyed with the stream it is used for. But now sink is released before the stream maintaing refcount consistency. This way we also avoid assigning anything to connector keeping all the operation local. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Roman Li authored
FBC enabling and disabling path has msleep which leads to BUG hit when called in atomic context, hence this patch replaces msleeps with udelays appropriately. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Mikita Lipski authored
Delete if statement that would force any display's color depth higher than 8 bpc to 8 Signed-off-by:
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Leo Liu authored
It should be stateless, and no need for scheduler to take care specially. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Deepak Sharma authored
Move logic of getting supported domain to a helper function Signed-off-by:
Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-by:
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Deepak Sharma authored
When vram size <= THRESHOLD(256M) lets use GTT for dumb buffer allocation. As SG will be enabled with vram size <= 256M scan out will not be an issue. v2: Use amdgpu_display_supported_domains to get supported domain. Signed-off-by:
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Mikita Lipski authored
Add case options to retrieve either physical or display clocks with voltage from SMU controller that are needed by display driver. Signed-off-by:
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Harry Wentland authored
Also drop wrong 10kHz comment Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Signed-off-by:
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- 25 May, 2018 4 commits
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Nayan Deshmukh authored
When checking for a dependency fence for belonging to the same entity compare it with scheduled as well finished fence. Earlier we were only comparing it with the scheduled fence. Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
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kbuild test robot authored
Fixes: 9b4c412a654c ("drm/amdgpu: Add static CG control for VCN on RV") Signed-off-by:kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
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Harry Wentland authored
This is required so we use the correct minimum clocks for Vega. Without this pplib will never be able to enter the lowest clock states. Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Last feature request for 4.18. Mostly vega20 support. - Vega20 support - clock and powergating for VCN - misc bug fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180524152427.32713-1-alexander.deucher@amd.com
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- 24 May, 2018 24 commits
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David Francis authored
In fixed31_32.h, in dc_fixpt_shl,'/' was used for division of one long long int by another long long int. As there is no inbuilt long long int division function in c, gcc inserted its own. However, gcc does not link the library that contains this function. To avoid this, use bitwise operators instead of / Reviewed-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Shaoyun Liu authored
Update to the latest version from the vbios team. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
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Alex Deucher authored
is_dpm_running callback was assigned to the same value twice. Drop the duplicate. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Emily Deng authored
To free the fence from the amdgpu_fence_slab, need twice call_rcu, to avoid the amdgpu_fence_slab_fini call kmem_cache_destroy(amdgpu_fence_slab) before kmem_cache_free(amdgpu_fence_slab, fence), add rcu_barrier after drm_sched_entity_fini. The kmem_cache_free(amdgpu_fence_slab, fence)'s call trace as below: 1.drm_sched_entity_fini -> drm_sched_entity_cleanup -> dma_fence_put(entity->last_scheduled) -> drm_sched_fence_release_finished -> drm_sched_fence_release_scheduled -> call_rcu(&fence->finished.rcu, drm_sched_fence_free) 2.drm_sched_fence_free -> dma_fence_put(fence->parent) -> amdgpu_fence_release -> call_rcu(&f->rcu, amdgpu_fence_free) -> kmem_cache_free(amdgpu_fence_slab, fence); v2:put the barrier before the kmem_cache_destroy v3:put the dma_fence_put(fence->parent) before call_rcu in drm_sched_fence_release_scheduled Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Christian König authored
Move all BOs belonging to a VM on the LRU with every submission. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Instead of sometimes checking if the vm_status is empty use the moved flag and also reset it when the BO leaves the state machine. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Christian König authored
In theory it is possible that PDs/PTs can move without eviction. Signed-off-by:
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Christian König authored
Splice the moved list to a local one to avoid taking the lock over and over again. Signed-off-by:
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Christian König authored
Use list_for_each_entry_safe here. v2: Drop the optimization, it doesn't work as expected. Signed-off-by:
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Christian König authored
Only the moved state needs a separate spin lock protection. All other states are protected by reserving the VM anyway. v2: fix some more incorrect cases Signed-off-by:
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Rex Zhu authored
Enable support for dynamically powering up/down VCN on demand. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
Enable static VCN powergating by default on Raven. Reviewed-by:
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Rex Zhu authored
Implement static powergating suport on VCN. Reviewed-by:
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Rex Zhu authored
Enable VCN clockgating by default on Raven. Reviewed-by:
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Rex Zhu authored
Implement proper static clockgating support for VCN. Reviewed-by:
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Rex Zhu authored
Add new macro to wait on a register field to be a specific value. Reviewed-by:
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Rex Zhu authored
Define new clock and powergating flags for VCN block. Reviewed-by:
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Rex Zhu authored
Add the powerplay callback for powergating VCN (same as UVD and VCE). Reviewed-by:
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Rex Zhu authored
VCN clockgating is handled manually like VCE and UVD. Reviewed-by:
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Rex Zhu authored
We should return unlock on the error path Reviewed-by:
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Rex Zhu authored
error: uninitialized symbol 'xxxx' Reviewed-by:
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Alex Deucher authored
The vbios mistakenly sets this bit on some boards without ECC. This can lead to reduced performance in some workloads. Disable the bit if the board does not have ECC. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Alex Deucher authored
Needed for proper memory setup depending on whether ECC is enabled on a particular board. Reviewed-by:
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Alex Deucher authored
The ForceParWrRMW setting needs to be enabled for ECC, but disabled when ECC is not enabled. Reviewed-by:
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