- 20 Mar, 2006 40 commits
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David S. Miller authored
On SUN4V, force IRQ state to idle in enable_irq(). However, I'm still not sure this is %100 correct. Call add_interrupt_randomness() on SUN4V too. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
On the PBM's first bus number, only allow device 0, function 0, to be poked at with PCI config space accesses. For some reason, this single device responds to all device numbers. Also, reduce the verbiage of the debugging log printk's for PCI cfg space accesses in the SUN4V PCI controller driver, so that it doesn't overwhelm the slow SUN4V hypervisor console. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
The trap code was calling itself :-) Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It just clutters up the log. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
That now gets done as a side effect of taking over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It doesn't like const variables being passed into "i" constraing asm operations. It's a bug, but there is nothing we can really do but work around it. Based upon a report from Andrew Morton. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
And check for errors at call sites. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
We should dynamically allocate the per-cpu pglist not use an in-kernel-image datum, since __pa() does not work on such addresses. Also, consistently use "u32" for devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Add udelay to polling console write loop, and increment the loop limit. Name the device "ttyHV" and pass that to add_preferred_console() when we're using hypervisor console. Kill sunhv_console_setup(), it's empty. Handle the case where we don't want to use hypervisor console. (ie. we have a head attached to a sun4v machine) Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
This is where we learn how to get the interrupts for things like the hypervisor console device. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
If the console is not for a particular Sun serial controller, set the drv->cons to NULL. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Need to use hypervisor calls instead of direct register accesses. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Get bus range from child of PCI controller root nexus. This is actually a hack, but the PCI-E bridge sitting at the top of the PCI tree responds to PCI config cycles for every device number, so best to just ignore it for now. Preliminary PCI irq routing, needs lots of work. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It is not PCI specific, it is for all system interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It has to be somewhere in the range from pbm->pci_first_busno to pbm->pci_last_busno, inclusive. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Clear top 8-bits of physical addresses in "ranges" property. This gives the actual physical address. Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
This handles the SUN4U vs SUN4V PTE layout differences with near zero performance cost. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
PCI cfg space is accessed transparently through the Hypervisor and not through direct cpu PIO operations. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
The bug that hit SUN4V TLB patching exists elsewhere. Make sure we cure all such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Writes by privileged code are not allowed. Signed-off-by: David S. Miller <davem@davemloft.net>
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