1. 15 Mar, 2011 3 commits
    • Liu Yu's avatar
      powerpc/85xx: Workaroudn e500 CPU erratum A005 · ac6f1203
      Liu Yu authored
      This erratum can occur if a single-precision floating-point,
      double-precision floating-point or vector floating-point instruction on a
      mispredicted branch path signals one of the floating-point data interrupts
      which are enabled by the SPEFSCR (FINVE, FDBZE, FUNFE or FOVFE bits).  This
      interrupt must be recorded in a one-cycle window when the misprediction is
      resolved.  If this extremely rare event should occur, the result could be:
      
      The SPE Data Exception from the mispredicted path may be reported
      erroneously if a single-precision floating-point, double-precision
      floating-point or vector floating-point instruction is the second
      instruction on the correct branch path.
      
      According to errata description, some efp instructions which are not
      supposed to trigger SPE exceptions can trigger the exceptions in this case.
      However, as we haven't emulated these instructions here, a signal will
      send to userspace, and userspace application would exit.
      
      This patch re-issue the efp instruction that we haven't emulated,
      so that hardware can properly execute it again if this case happen.
      Signed-off-by: default avatarLiu Yu <yu.liu@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      ac6f1203
    • Prabhakar Kushwaha's avatar
      powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x · f4154e16
      Prabhakar Kushwaha authored
      FSL PCIe controller v2.1:
           - New MSI inbound window
           - Same Inbound windows address as PCIe controller v1.x
      
      Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
      
      FSL PCIe controller v2.2 and v2.3:
           - Different addresses for PCIe inbound window 3,2,1
           - Exposed PCIe inbound window 0
           - New PCIe interrupt status register
      
      Added new config and interrupt Status register to struct ccsr_pci & updated
      pit_t array size to reflect the 4 inbound windows.
      
      Device tree is used to maintain backward compatibility i.e. update inbound
      window 1 index depending upon "compatible" field witin PCIE node.
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Acked-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f4154e16
    • Kumar Gala's avatar
      powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e · decbb280
      Kumar Gala authored
      If the spin table is located in the linear mapping (which can happen if
      we have 4G or more of memory) we need to access the spin table via a
      cacheable coherent mapping like we do on ppc32 (and do explicit cache
      flush).
      
      See the following commit for the ppc32 version of this issue:
      
      commit d1d47ec6
      Author: Peter Tyser <ptyser@xes-inc.com>
      Date:   Fri Dec 18 16:50:37 2009 -0600
      
          powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      decbb280
  2. 11 Mar, 2011 1 commit
  3. 10 Mar, 2011 28 commits
  4. 04 Mar, 2011 4 commits
  5. 02 Mar, 2011 4 commits