- 27 Jul, 2022 2 commits
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Anusha Srivatsa authored
Cleanup the intel_phy_is_combo to accommodate for cases where combo phy is not available. v2: retain comment that explains DG2 returning false from intel_phy_is_combo() (Arun) Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Arun R Murthy <arun.r.murthy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220725225028.98612-1-anusha.srivatsa@intel.com
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Ankit Nautiyal authored
HDMI2.1 requires some higher resolution video modes to be enumerated only if HDMI2.1 Fixed Rate Link (FRL) is supported. Current platforms do not support FRL transmission so prune modes that require HDMI2.1 FRL. v2: Fixed the condition to check for dotclock > 600. Return MODE_CLOCK_HIGH as mode status. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> (v1) Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220721084645.3411219-1-ankit.k.nautiyal@intel.com
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- 19 Jul, 2022 1 commit
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Swati Sharma authored
Add debug print statement to print scaler filter property value. Since property can be set as either default or integer scaler; its good if we can get debug print for the same in dmesg log. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by:
Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
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- 18 Jul, 2022 3 commits
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José Roberto de Souza authored
The issue here was on for_each_intel_encoder_mask_with_psr() over the new_crtc_state encoder mask, so if the CRTC was being disabled mask would be zero and it would not have any chance to disable PSR. So here doing for_each_intel_encoder_mask_with_psr() over the old_crtc_state encoder mask and then using the new_crtc_state to check if PSR needs to be disabled. Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220714150755.154985-2-jose.souza@intel.com
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José Roberto de Souza authored
This patches fixes a issue but not in the right way as for_each_oldnew_intel_crtc_in_state() will interate over all CRTCs not only the crtc passed as parameter, also this two for_each loops are not necessary and only make code harder to understand. Proper fix will be discussed in the next patch. This reverts commit 75f66490. Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Imre Deak authored
Starting with TGL the disabling order of HDMI transcoder clock vs. DDI BUF has swapped, fix this. There hasn't been any issues seen related to this, but let's follow the spec. Reported-by:
Sandeep K Lakkakula <sandeep.k.lakkakula@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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- 12 Jul, 2022 2 commits
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Matt Roper authored
We already disable FBC when PSR2 is enabled on display version 12 and above; this new workaround now requires that we do the same with PSR1 on display versions 12 and 13. Signed-off-by:
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Jouni Högander authored
Currently PSR is left enabled when all planes are disabled if there is no attached encoder in new state. This seems to be causing FIFO underruns. Fix this by checking if encoder exists in new crtc state and disable PSR if it doesn't. v2: Unify disable logic with existing Cc: Mika Kahola <mika.kahola@intel.com> Reported-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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- 08 Jul, 2022 1 commit
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Stanislav Lisovskiy authored
We seem to need this W/A same way as for TGL, in order to fix some of the underruns, which we currently have and those not related to PSR. Signed-off-by:
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- 06 Jul, 2022 3 commits
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Ville Syrjälä authored
JSP is based on ICP and we don't really need to differentiate between the two. So let's just delcare JSP to be ICP. The only slight change here is for Wa_14011294188 which we used to apply for JSP but now we'll only apply to MCC. This should be fine since the issue being dealt with was introduced in TGP and inherited into MCC. JSP being derived from ICP should not need this workaround. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220630150600.24611-4-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
MCC is derived from TGP, and we have no real need to differentiate between the two. Thus remove PCH_MCC and just declare it to be PCH_TGP compatible. Signed-off-by:
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Ville Syrjälä authored
The comments regarding PCH compatibility use long vs. short names inconsistently. Just use short names always. Signed-off-by:
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- 01 Jul, 2022 1 commit
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Tom Rix authored
spelling changes resoluition -> resolution dont -> don't commmit -> commit Invalidade -> Invalidate Signed-off-by:
Tom Rix <trix@redhat.com> Reviewed-by:
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- 30 Jun, 2022 3 commits
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José Roberto de Souza authored
Display is turned off by i915_drm_suspend() during the suspend procedure, removing the last reference of some gem objects that were used by display. The issue is that those objects are only actually freed when mm.free_work executed and that can happen very late in the suspend process causing issues. So here draining all freed objects released by display fixing suspend issues. Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220629134721.48375-1-jose.souza@intel.com
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Jani Nikula authored
We've just set up device info in i915_driver_create() so we can use DISPLAY_VER() intead of looking at match_info directly. Semantically we want to check the display version instead of the graphics version, and for the earlier platforms they are always the same. v2: Use DISPLAY_VER() instead of GRAPHICS_VER() (Ville) Signed-off-by:
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Jani Nikula authored
The ddc pin and aux channel sanitization may disable DVI/HDMI and DP, respectively, of ports parsed earlier, in "last one wins" fashion. With parsing and printing interleaved, we'll end up logging support first and disabling later anyway. Now that we've split ddi port info parsing and printing, take it further by doing the printing in a separate loop, fixing the logging. Note that this also changes the logging order from VBT child device order to port number order. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 28 Jun, 2022 2 commits
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Hangyu Hua authored
If drm_connector_init fails, intel_connector_free will be called to take care of proper free. So it is necessary to drop the refcount of port before intel_connector_free. Fixes: 091a4f91 ("drm/i915: Handle drm-layer errors in intel_dp_add_mst_connector") Signed-off-by:
Hangyu Hua <hbh25y@gmail.com> Reviewed-by:
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Dan Carpenter authored
This function is supposed to return zero or negative error codes but it accidentally returns true on failure. Fixes: 92a02074 ("drm/i915: Split shared dpll .get_dplls() into compute and get phases") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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- 27 Jun, 2022 11 commits
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Ville Syrjälä authored
The LUTs are a display feature so move the details into the display portion of the device info. Signed-off-by:
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Ville Syrjälä authored
XE_LPD_CURSOR_OFFSETS is a duplicate of TGL_CURSOR_OFFSETS. Just use the latter. Signed-off-by:
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Ville Syrjälä authored
Stop hand rolling _MMIO_TRANS2() and just use the real thing. Note that this register isn't even used atm, hence why this builds despite the _PIPE2() macro not actually existing. Signed-off-by:
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Ville Syrjälä authored
Stop hand rolling _MMIO_TRANS2() and just use the real thing. Signed-off-by:
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Ville Syrjälä authored
The other similar macros have the _MMIO prefix, so give it also to _CURSOR2. Signed-off-by:
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Ville Syrjälä authored
Using a signed type for the register offsets doesn't really make sense. Switch to u32. Signed-off-by:
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Ville Syrjälä authored
The display register offsets are display stuff so stick into the display portion of the device info. Signed-off-by:
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Ville Syrjälä authored
The display register offsets are display stuff so stick into the display portion of the device info. Signed-off-by:
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Ville Syrjälä authored
DBUF is a display thing, so move it into the display portion of the device info. Signed-off-by:
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Ville Syrjälä authored
Eliminate the PIPECONF RMWs from .comit_commit() so that we can finally declare the whole vblank evade part (and the noarm() part) of the pipe commit free of register reads. Or at least I hope that's the last read... Only the i9xx/ilk codepaths need this for now, but let's add the same thing for hsw+ just in case we want to start calling that during fastsets at some point (eg. to change dithering settings/etc.). Should open up the way to start experimenting with different DSB usage approaches for pipe commits. Signed-off-by:
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Anshuman Gupta authored
Currently i915 disables d3cold for i915 pci dev. This blocks D3 for i915 gfx pci upstream bridge (VSP). Let's disable d3cold at gfx root port to make sure that i915 gfx VSP can transition to D3 to save some power. We don't need to disable/enable d3cold in rpm, s2idle suspend/resume handlers. Disabling/Enabling d3cold at gfx root port in probe/remove phase is sufficient. Fixes: 1a085e23 ("drm/i915: Disable D3Cold in s2idle and runtime pm") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by:
Badal Nilawar <badal.nilawar@intel.com> Acked-by:
: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220616122249.5007-1-anshuman.gupta@intel.com
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- 23 Jun, 2022 1 commit
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José Roberto de Souza authored
When the last reference of a gem object is removed it is added to the mm.free_list list and mm.free_work is queued to actually free the object. So gem objects that had their last reference removed by display during drm_atomic_helper_shutdown() are added to mm.free_list what could cause that mm.free_work is executed at the same time as intel_runtime_pm_driver_release() causing raw-wakerefs warning. So here only calling i915_gem_suspend() and by consequence i915_gem_drain_freed_objects() only after display is down making sure all display gem objecs are freed when intel_runtime_pm_driver_release() is executed. Signed-off-by:
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- 20 Jun, 2022 4 commits
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Animesh Manna authored
Each LFP may have different panel type which is stored in LFP data data block. Based on the child device index respective panel-type/ panel-type2 field will be used. v1: Initial rfc verion. v2: Based on review comments from Jani, - Used panel-type instead addition panel-index variable. - DEVICE_HANDLE_* name changed and placed before DEVICE_TYPE_* macro. v3: - passing intel_bios_encoder_data as argument of intel_bios_init_panel(). Passing NULL to indicate encoder is not initialized yet for dsi as current focus is to enable dual EDP. [Jani] v4: - encoder->devdata used which is initialized before from vbt structure. [Jani] Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Reviewed-by:
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Jani Nikula authored
Pass struct drm_i915_private * instead of struct drm_device *, and rename dev_priv to i915. v2: Rebase Signed-off-by:
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Jani Nikula authored
Split out the modeset hardware state readout and sanitize, or state setup, to a separate file. Do some drive-by checkpatch fixes while at it. v2: Rebase Signed-off-by:
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Jason A. Donenfeld authored
This reverts commit 73867c87 ("drm/i915/display: Remove check for low voltage sku for max dp source rate"), which, on an i7-11850H iGPU with a Thinkpad X1 Extreme Gen 4, attached to a LG LP160UQ1-SPB1 embedded panel, causes wild flickering glitching technicolor pyrotechnics on resumption from suspend. The display shows strobing colors in an utter disaster explosion of pantone, as though bombs were dropped on the leprechauns at the base of the rainbow. Rebooting the machine fixes the issue, presumably because the display is initialized by firmware rather than by i915. Otherwise, the GPU appears to work fine. Bisection traced it back to this commit, which makes sense given the issues. Note: This re-opens, and puts back to the drawing board, https://gitlab.freedesktop.org/drm/intel/-/issues/5272 which was fixed by the regressing commit. Fixes: 73867c87 ("drm/i915/display: Remove check for low voltage sku for max dp source rate") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6205 Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jani Saarinen <jani.saarinen@intel.com> Signed-off-by:
Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by:
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- 17 Jun, 2022 6 commits
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Jani Nikula authored
Prefer struct drm_i915_private *i915 over struct drm_device or dev_priv. Signed-off-by:
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Jani Nikula authored
Rename dev_priv to i915 in crtc state dumping code. Signed-off-by:
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Jani Nikula authored
Add the brackets [] around crtc state dump context string in intel_crtc_state_dump() so the callers don't have to. Signed-off-by:
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Jani Nikula authored
Declutter intel_display.c by splitting out crtc state dumping to a separate file. v2: intel_pipe_config_dump -> intel_crtc_state_dump Signed-off-by:
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Jani Nikula authored
Add new file intel_modeset_verify.c for high level modeset verification code to declutter intel_display.h. The new file is supposed to be about crtc/encoder/connector verification; the state verification for very specific functionality such as plls or wm should be placed next to the code it verifies. Fix some minor checkpatch issues while at it. v2: Rebase Signed-off-by:
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Jani Nikula authored
Keep the mpllb implementation details together in intel_snps_phy.c. Also declutter intel_display.c. v2: intel_mpllb_verify_state -> void intel_mpllb_state_verify (Ville) Signed-off-by:
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