- 09 Apr, 2021 40 commits
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Qingqing Zhuo authored
[Why] DCN3 is not reusing DCN1 mask_sh_list, causing SURFACE_FLIP_INT_MASK missing in the mapping. [How] Add the corresponding entry to DCN3 list. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Wayne Lin authored
[Why] Commit 1c85f3db ("drm/amd/display: Add kernel doc to crc_rd_wrk field") adds kernel doc for crc_rd_wrk field in amdgpu_dm.h but it's incorrectly formatted. Make htmldocs warns: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:398: warning: Incorrect use of kernel-doc format: * @crc_rd_wrk [How] Tweak the kernel doc for crc_rd_wrk. Fixes: 1c85f3db ("drm/amd/display: Add kernel doc to crc_rd_wrk field") Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Mikita Lipski authored
[why/how] Due to compiler optimization the values would be passed to the division function uninitialized causing a div by zero. Initialize the numerator and denominator to 0 and 1 to prevent division by zero. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
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Victor Lu authored
[why] Currently to view the DCC_EN bit the entire DTN log must be dumped. A compact method to view the DCC_EN bit is desirable. [how] Introduce new debugfs interface that only dumps the DCC_EN bit. Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Harry Wentland authored
[Why&How] Add debug flag for an option to disable min fclk. Signed-off-by:
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Harry Wentland authored
[Why&How] Add debug prints for SMU messages with regard to versions, clocks, and more. Signed-off-by:
Robin Singh <Robin.Singh@amd.com> Acked-by:
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Jake Wang authored
[Why] We need to keep track of the number of eDP links to properly enumerate edp panel control instance. [How] Added dc_edp_id_count to dc_context to keep track of number of eDP links. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why] Functionality of LTTPR is reporter through the DPCD register [How] Expose a interface in debugfs to read the current status of LTTPR as reported from the device's DPCD register Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Leo Li authored
[Why] The OTG_VUPDATE_KEEPOUT register and fields is available on DCN10, and named the same in DCN20. [How] Move register definition and programming function to dcn10 optc. There is no functional change. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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Robin Singh authored
[why] There is case when the userspace like IGT test updates the custom timings, i.e. the number of active lines CRTC property value, and without committing the change, followed by resetting the display, creating FB and plane to the pipe and committing. The NULL pointer of pipe_ctx->plane_state occurs and result in kernel crash. We need to avoid that. [how] add pointer check for the dc_plane_state of the pipe context in the call of committing planes for stream in DC component. Signed-off-by:
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David (Dingchen) Zhang authored
[why] In MST setup, we'd use MST downstream AUX to dump the DPRX CRCs from sink device. [how] Assign the mst_port->aux to read DPCD registers. Signed-off-by:David (Dingchen) Zhang <dingchen.zhang@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Today a parameter is passed to dmub_srv_send_gpint_command which specifies the max amount of time to wait for the command to be acked. This parameter instead specifies the number of times to check if the command was acked. We wish to add a lower bound to the timeout, which can be accomplished by using a delay or a timestamp. It has been decided to use udelay instead of a timestamp simply because we don't want to expose a high precision counter if it doesn't yield large benefits. [How] Add udelay(1) between each for loop iteration. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] GPINT command to get PSR state from FW times out. [How] Add retry to get valid PSR state. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Hawking Zhang authored
gfx ras is only available in cerntain ip generations. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
John Clements <John.Clements@amd.com> Signed-off-by:
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Hawking Zhang authored
mmhub ras is only avaiable in cerntain mmhub ip generation. Signed-off-by:
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Hawking Zhang authored
df/mca ras is not managed by gpu driver when gpu is connected to cpu through xgmi. gpu driver should register x86 mca notifier for umc ras error notification Signed-off-by:
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Hawking Zhang authored
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver only initializes umc ras callbacks when it manages umc ras. Signed-off-by:
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Hawking Zhang authored
xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver only initializes xgmi ras functions when it manages xgmi ras. Signed-off-by:
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Hawking Zhang authored
nbio ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split nbio callbacks into ras and non-ras ones so gpu driver only initializes nbio ras callbacks when it manages nbio ras. Signed-off-by:
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Hawking Zhang authored
query_ras_error_address will be invoked to query bad page address when there is poison data in HBM consumed by GPU engines. Signed-off-by:
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Hawking Zhang authored
umc query_ras_error_count will be invoked to query umc correctable and uncorrectable error. It will reset the umc ras error counter after the query. Signed-off-by:
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Hawking Zhang authored
Add helper functions to query correctable and uncorrectable umc ras error. Signed-off-by:
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Hawking Zhang authored
umc_v6_7_funcs are callbacks to support umc ras functionalities in aldebaran Signed-off-by:
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Hawking Zhang authored
Driver only manages GFX/SDMA/MMHUB RAS in platforms that gpu node is connected to cpu through XGMI, other than that, it queries VBIOS for RAS capabilities. Signed-off-by:
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Amber Lin authored
Power Management IP is initialized/enabled before KFD init. When a thermal throttling happens before kfd_smi_init is done, calling the KFD SMI update function causes a stack dump by referring a NULL pointer ( smi_clients list). Check if kfd_init is completed before calling the function. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Wan Jiabing authored
struct mod_hdcp is declared twice. One is declared at 33rd line. The blew one is not needed. Remove the duplicate. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Signed-off-by:
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Alex Deucher authored
These were leftover from the old CI dpm code which was retired a while ago. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Bernard Zhao authored
Fix patch check warning: WARNING: suspect code indent for conditional statements (8, 17) + if (obj && obj->use < 0) { + DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); WARNING: braces {} are not necessary for single statement blocks + if (obj && obj->use < 0) { + DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); + } Signed-off-by:Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Bernard Zhao authored
Fix patch check warning: WARNING: Prefer kmalloc_array over kmalloc with multiply + buf = kmalloc(MAX_KFIFO_SIZE * sizeof(*buf), GFP_KERNEL); Signed-off-by:
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Stanley.Yang authored
Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reivewed-by:
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Philip Yang authored
Forgot to reserve a fence slot to use sdma to update page table, cause below kernel BUG backtrace to handle vm retry fault while application is exiting. [ 133.048143] kernel BUG at /home/yangp/git/compute_staging/kernel/drivers/dma-buf/dma-resv.c:281! [ 133.048487] Workqueue: events amdgpu_irq_handle_ih1 [amdgpu] [ 133.048506] RIP: 0010:dma_resv_add_shared_fence+0x204/0x280 [ 133.048672] amdgpu_vm_sdma_commit+0x134/0x220 [amdgpu] [ 133.048788] amdgpu_vm_bo_update_range+0x220/0x250 [amdgpu] [ 133.048905] amdgpu_vm_handle_fault+0x202/0x370 [amdgpu] [ 133.049031] gmc_v9_0_process_interrupt+0x1ab/0x310 [amdgpu] [ 133.049165] ? kgd2kfd_interrupt+0x9a/0x180 [amdgpu] [ 133.049289] ? amdgpu_irq_dispatch+0xb6/0x240 [amdgpu] [ 133.049408] amdgpu_irq_dispatch+0xb6/0x240 [amdgpu] [ 133.049534] amdgpu_ih_process+0x9b/0x1c0 [amdgpu] [ 133.049657] amdgpu_irq_handle_ih1+0x21/0x60 [amdgpu] [ 133.049669] process_one_work+0x29f/0x640 [ 133.049678] worker_thread+0x39/0x3f0 [ 133.049685] ? process_one_work+0x640/0x640 Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Peng Ju Zhou authored
1. expand rlcg interface for gc & mmhub indirect access 2. add rlcg interface for no kiq v2: squash in fix for gfx9 (Changfeng) Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by:
Emily.Deng <Emily.Deng@amd.com> Signed-off-by:
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Peng Ju Zhou authored
using the control bits got from host to control registers access. Signed-off-by:
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Peng Ju Zhou authored
get pf2vf msg info at it's earliest time so that guest driver can use these info to decide whether register indirect access enabled. Signed-off-by:
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Peng Ju Zhou authored
unify host driver and guest driver indirect access control bits names Signed-off-by:
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Alex Deucher authored
Use uintptr_t rather than uint64_t. Reviewed-by:
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Xℹ Ruoyao authored
The page table of AMDGPU requires an alignment to CPU page so we should check ioctl parameters for it. Return -EINVAL if some parameter is unaligned to CPU page, instead of corrupt the page table sliently. Reviewed-by:
Xi Ruoyao <xry111@mengyan1223.wang> Signed-off-by:
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Huacai Chen authored
In Mesa, dev_info.gart_page_size is used for alignment and it was set to AMDGPU_GPU_PAGE_SIZE(4KB). However, the page table of AMDGPU driver requires an alignment on CPU pages. So, for non-4KB page system, gart_page_size should be max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE). Signed-off-by:
Rui Wang <wangr@lemote.com> Signed-off-by:
Huacai Chen <chenhc@lemote.com> Link: https://github.com/loongson-community/linux-stable/commit/caa9c0a1 [Xi: rebased for drm-next, use max_t for checkpatch, and reworded commit message.] Signed-off-by:
Dan Horák <dan@danny.cz> Reviewed-by:
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Guchun Chen authored
Leverage the same logic from amdgpu_ttm_tt_unpin_userptr. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); v2: put short variable declaration last Signed-off-by:
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