- 16 Sep, 2019 40 commits
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Jean Delvare authored
It is fine for displays without audio functionality to not provide any SAD block in their EDID. Do not log an error in that case, just return quietly. This fixes half of bug fdo#107825: https://bugs.freedesktop.org/show_bug.cgi?id=107825Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Trek authored
Do not try to allocate any amount of memory requested by the user. Instead limit it to 128 registers. Actually the longest series of consecutive allowed registers are 48, mmGB_TILE_MODE0-31 and mmGB_MACROTILE_MODE0-15 (0x2644-0x2673). Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111273Signed-off-by:
Trek <trek00@inbox.ru> Signed-off-by:
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Hans de Goede authored
Bail from the pci_driver probe function instead of from the drm_driver load function. This avoid /dev/dri/card0 temporarily getting registered and then unregistered again, sending unwanted add / remove udev events to userspace. Specifically this avoids triggering the (userspace) bug fixed by this plymouth merge-request: https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 Note that despite that being an userspace bug, not sending unnecessary udev events is a good idea in general. BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in the variable name eanble, rename it to enable. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Kent Russell authored
This reverts commit e01f2d41. VG20 did not require this workaround, as the fix is in the VBIOS. Leave VG10/12 workaround as some older shipped cards do not have the VBIOS fix in place, and the kernel workaround is required in those situations Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Next step towards HMM support. For now just silence the retry fault and optionally redirect the request to the dummy page. v2: make sure the VM is not destroyed while we handle the fault. v3: fix VM destroy check, cleanup comments Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Christian König authored
Free the pasid only while the root PD is reserved. This prevents use after free in the page fault handling. Signed-off-by:
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Christian König authored
While handling a page fault we can't wait for other ongoing GPU operations or we can potentially run into deadlocks. Signed-off-by:
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Christian König authored
For handling PD/PT clears directly in the fault handler. Signed-off-by:
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Christian König authored
For handling PTE updates directly in the fault handler. Signed-off-by:
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Christian König authored
For handling PDE updates directly in the fault handler. v2: fix typo in comment Signed-off-by:
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Christian König authored
This allows us to update page tables directly while in a page fault. v2: use direct/delayed entities and still wait for moves Signed-off-by:
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Christian König authored
For page fault handling we need to use a direct update which can't be blocked by ongoing user CS. Signed-off-by:
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Christian König authored
Setting the no_gpu_wait flag means that the allocate BO must be available immediately and we can't wait for any GPU operation to finish. v2: squash in mem leak fix, rebase Signed-off-by:
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Christian König authored
Need to make sure that we actually dropping the right fence. Could be done with RCU as well, but to complicated for a fix. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Jiange Zhao authored
In SRIOV case, the autoload sequence is the same as bare metal, except VF won't load TOC. Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Jiange Zhao authored
In SRIOV case, SMU and powerplay are handled in HV. VF shouldn't have control over SMU and powerplay. Signed-off-by:
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Prike Liang authored
The sdma_v4 should be ungated when the IP resume back, otherwise it will hang up and resume time out error. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Jiange Zhao authored
Mailbox functions and interrupts are only for Navi12 VF. Register functions and irqs during initialization. Reviewed-by:
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Jack Zhang authored
psp v11 code missed ring stop in ring create function(VMR) while psp v3.1 code had the code. This will cause VM destroy1 fail and psp ring create fail. For SIOV-VF, ring_stop should not be deleted in ring_create function. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Evan Quan authored
This is especially needed for non-psp loading way. Signed-off-by:
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Evan Quan authored
Set mp1 state properly for SW SMU suspend/reset routine. Signed-off-by:
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Felix Kuehling authored
Hawaii needs to flush caches explicitly, submitting an IB in a user VMID from kernel mode. There is no s_fence in this case. Fixes: eb3961a5 ("drm/amdgpu: remove fence context from the job") Signed-off-by:
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Andrey Grodzovsky authored
Problem: amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu because writing to EEPROM during ASIC reset was unstable. But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called directly from ISR context and so locking is not allowed. Also it's irrelevant for this partilcular interrupt as this is generic RAS interrupt and not memory errors specific. Fix: Avoid calling amdgpu_ras_reserve_bad_pages if not in task context. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Jiange Zhao authored
Mimic the ones for Vega10, add mailbox backend for Navi1x Reviewed-by:
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Guchun Chen authored
ras error query funtionality implementation Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Guchun Chen authored
These registers will be accessed for querying ras errors. Signed-off-by:
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Guchun Chen authored
Call pcie bif ras query/inject in amdgpu ras. Signed-off-by:
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Guchun Chen authored
Add the interface query_ras_error_count for nbio. Signed-off-by:
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Tianci.Yin authored
add and_mask since the programming logic of golden setting changed Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Hawking Zhang authored
allow inject error to XGMI block via debugfs node ras_ctrl Signed-off-by:
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Hawking Zhang authored
init ras common interface and fs node for xgmi block v2: remove unnecessary physical node number check before invoking amdgpu_xgmi_ras_late_init Signed-off-by:
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Huang Rui authored
This patch fixes null pointer issue below, I missed to init the asic renior name while I rebase the patches. [ 106.004250] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 106.004254] #PF: supervisor read access in kernel mode [ 106.004256] #PF: error_code(0x0000) - not-present page [ 106.004257] PGD 0 P4D 0 [ 106.004261] Oops: 0000 [#1] SMP NOPTI [ 106.004264] CPU: 3 PID: 1422 Comm: modprobe Not tainted 5.2.0-rc1-custom #1 [ 106.004266] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS WCD9814N_Weekly_19_08_1 08/14/2019 [ 106.004272] RIP: 0010:strncpy+0x12/0x30 [ 106.004274] Code: c1 c0 11 48 c1 c6 15 48 31 d0 48 c1 c2 20 31 c2 89 d0 31 f0 41 5c 5d c3 55 48 85 d2 48 89 f8 48 89 e5 74 1e 48 01 fa 48 89 f9 <44> 0f b6 06 41 80 f8 01 44 88 01 48 83 de ff 48 83 c1 01 48 39 d1 [ 106.004278] RSP: 0018:ffffc092c1fd37a8 EFLAGS: 00010286 [ 106.004281] RAX: ffff9e943466a28c RBX: 00000000000036ed RCX: ffff9e943466a28c [ 106.004283] RDX: ffff9e943466a2ac RSI: 0000000000000000 RDI: ffff9e943466a28c [ 106.004285] RBP: ffffc092c1fd37a8 R08: ffff9e943d100000 R09: 0000000000000228 [ 106.004287] R10: ffff9e94418dc5a8 R11: ffff9e944746c0d0 R12: 0000000000000000 [ 106.004289] R13: ffff9e943fa1ec00 R14: ffff9e943466a200 R15: ffff9e943466a200 [ 106.004291] FS: 00007f7a022c5540(0000) GS:ffff9e9447ac0000(0000) knlGS:0000000000000000 [ 106.004294] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 106.004296] CR2: 0000000000000000 CR3: 00000001ff0b0000 CR4: 0000000000340ee0 [ 106.004298] Call Trace: [ 106.004382] kfd_topology_add_device+0x150/0x610 [amdgpu] [ 106.004445] kgd2kfd_device_init+0x2e0/0x4f0 [amdgpu] [ 106.004509] amdgpu_amdkfd_device_init+0x14c/0x1b0 [amdgpu] Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-and-Tested-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] we only want the lowest voltage to be available for dali. [How] Use the get_highest_allowed_voltage_level function to return 0 for dali Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Dali is a new asic revision based on raven2 Add the ID and ASICREV_IS_DALI define Signed-off-by:
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Andrey Grodzovsky authored
The table grows quickly during debug/development effort when multiple RAS errors are injected. Allow to avoid this by setting table header back to empty if needed. v2: Switch to debugfs entry instead of load time parameter. Signed-off-by:
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Andrey Grodzovsky authored
This will allow to reset the table on the fly. Signed-off-by:
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Tao Zhou authored
this interface is related to specific version of umc, distinguish it from ras_late_init Signed-off-by:
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Tao Zhou authored
move umc ras init from ras module to umc block, generic ras module should pay less attention to specific ras block. Signed-off-by:
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Tao Zhou authored
umc late init is umc specific, it's more suitable to be put in umc block Signed-off-by:
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