- 19 May, 2020 27 commits
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Oded Gabbay authored
Enable the GAUDI ASIC code in the pci probe callback of the driver so the driver will handle GAUDI ASICs. Signed-off-by:Oded Gabbay <oded.gabbay@gmail.com>
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Omer Shpigelman authored
Add the GAUDI code to initialize the ASIC's profiler. The profile receives its initialization values from the user, same as in Goya, but the code to initialize is in the driver because the configuration space of the device is not directly exposed to the user. Signed-off-by:
Omer Shpigelman <oshpigelman@habana.ai> Reviewed-by:
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Omer Shpigelman authored
Add the code to initialize the security module of GAUDI. Similar to Goya, we have two dedicated mechanisms for security: Range Registers and Protection bits. Those mechanisms protect sensitive memory and configuration areas inside the device. In addition, in Gaudi we moved to a 3-level security scheme, where the F/W runs with the highest security level (Privileged), the driver runs with a less secured level (Secured) and the user is neither privileged nor secured. The security module in the driver configures the Secured parts so the user won't be able to access them. The Privileged parts are configured by the F/W. Signed-off-by:
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Oded Gabbay authored
The hwmgr module is responsible for messages sent to GAUDI F/W that are not common to all habanalabs ASICs. In GAUDI, we provide the user a simplified mode of controlling the ASIC clock frequency. Instead of three different clocks, we present a single clock property that the user can configure via sysfs. Signed-off-by: -
Oded Gabbay authored
Add the ASIC-dependent code for GAUDI. Supply (almost) all of the function callbacks that the driver's common code need to initialize, finalize and submit workloads to the GAUDI ASIC. It also contains the code to initialize the F/W of the GAUDI ASIC and to receive events from the F/W. Signed-off-by: -
Oded Gabbay authored
Add the new defines for GAUDI uapi interface. It includes the queue IDs, the engine IDs, SRAM reserved space and Sync Manager reserved resources. There is no new IOCTL or additional operations in existing IOCTLs. Signed-off-by: -
Oded Gabbay authored
Add the relevant GAUDI ASIC registers header files. These files are generated automatically from a tool maintained by the VLSI engineers. There are more files which are not upstreamed because only very few defines from those files are used in the driver. For those files, we copied the relevant defines into gaudi_regs.h and gaudi_masks.h, to reduce the size of this patch. Signed-off-by: -
Omer Shpigelman authored
For Gaudi the driver gets two new additional properties from the F/W: 1. The card's type - PCI or PMC 2. The card's location in the Gaudi's box (relevant only for PMC). The card's location is also passed to the user in the HW IP info structure as it needs this property for establishing communication between Gaudis. Signed-off-by:
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Oded Gabbay authored
In Gaudi there is a feature of clock gating certain engines. Therefore, add this property to the device structure. In addition, due to a limitation of this feature, the driver needs to dynamically enable or disable this feature during run-time. Therefore, add ASIC interface functions to enable/disable this function from the common code. Moreover, this feature must be turned off when the user wishes to debug the ASIC by reading/writing registers and/or memory through the driver's debugfs. Therefore, add an option to enable/disable clock gating via the debugfs interface. Signed-off-by: -
Oded Gabbay authored
For Gaudi, the driver doesn't change the PM profile automatically due to device-controlled PM capabilities. Therefore, set the PM profile to auto only for Goya so the driver's code to automatically change the profile won't run on Gaudi. Signed-off-by: -
Omer Shpigelman authored
Gaudi requires longer waiting during reset due to closing of network ports. Add this explanation to the relevant comment in the code and add a dedicated define for this reset timeout period, instead of multiplying another define. Signed-off-by:
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Omer Shpigelman authored
Coresight is not supported on simulator, therefore add a boolean for checking that (currently used by un-upstreamed code). Signed-off-by:
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Omer Shpigelman authored
Add the following two operations to the CS IOCTL: Signal: The signal operation is basically a command submission, that is created by the driver upon user request. It will be implemented using a dedicated PQE that will increment a specific SOB. There will be a new flag: HL_CS_FLAGS_SIGNAL. When the user set this flag in the CS IOCTL structure, the driver will execute a dedicated code path that will prepare this special PQE and submit it. The user only needs to provide a queue index on which to put the signal. Wait: The wait operation is also a command submission that is created by the driver upon user request. It will be implemented using a dedicated PQE that will contain packets of "ARM a monitor" + FENCE packet. There will be a new flag: HL_CS_FLAGS_WAIT. When the user set this flag in the CS structure, the driver will execute a dedicated code path that will prepare this special PQE and submit it. The user needs to provide the following parameters: 1. queue ID 2. an array of signal_seq numbers and the number of signals to wait on (the length of signal_seq_arr). The IOCTL will return the CS sequence number of the wait it put on the queue ID. Currently, the code supports signal_seq_nr==1. But this API definition will allow us to put a single PQE that waits on multiple signals. To correctly configure the monitor and fence, the driver will need to retrieve the specified signal CS object that contains the relevant SOB and its expected value. In case the signal CS has already been completed, there is no point of adding a wait operation. In this case, the driver will return to the user *without* putting anything on the PQ. The return code should reflect to the user that the signal was completed, as we won't return a CS sequence number for this wait. Signed-off-by:
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Omer Shpigelman authored
Define a structure representing the h/w sync object (SOB). a SOB can contain up to 2^15 values. Each signal CS will increment the SOB by 1, so after some time we will reach the maximum number the SOB can represent. When that happens, the driver needs to move to a different SOB for the signal operation. A SOB can be in 1 of 4 states: 1. Working state with value < 2^15 2. We reached a value of 2^15, but the signal operations weren't completed yet OR there are pending waits on this signal. For the next submission, the driver will move to another SOB. 3. ALL the signal operations on the SOB have finished AND there are no more pending waits on the SOB AND we reached a value of 2^15 (This basically means the refcnt of the SOB is 0 - see explanation below). When that happens, the driver can clear the SOB by simply doing WREG32 0 to it and set the refcnt back to 1. 4. The SOB is cleared and can be used next time by the driver when it needs to reuse an SOB. Per SOB, the driver will maintain a single refcnt, that will be initialized to 1. When a signal or wait operation on this SOB is submitted to the PQ, the refcnt will be incremented. When a signal or wait operation on this SOB completes, the refcnt will be decremented. After the submission of the signal operation that increments the SOB to a value of 2^15, the refcnt is also decremented. Signed-off-by:
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Omer Shpigelman authored
This feature requires handling h/w resources which are a bit different from one ASIC to the other. Therefore, we need to define a set of interfaces the ASIC code provides to the common code to signal, wait, reset sync object and to reset and init a queue. As this feature is not supported in Goya, provide an empty implementation of those functions. Signed-off-by:
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Omer Shpigelman authored
This is a pre-requisite to upstreaming GAUDI support. Signal/wait operations are done by the user to perform sync between two Primary Queues (PQs). The sync is done using the sync manager and it is usually resolved inside the device, but sometimes it can be resolved in the host, i.e. the user should be able to wait in the host until a signal has been completed. The mechanism to define signal and wait operations is done by the driver because it needs atomicity and serialization, which is already done in the driver when submitting work to the different queues. To implement this feature, the driver "takes" a couple of h/w resources, and this is reflected by the defines added to the uapi file. The signal/wait operations are done via the existing CS IOCTL, and they use the same data structure. There is a difference in the meaning of some of the parameters, and for that we added unions to make the code more readable. Signed-off-by:
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Oded Gabbay authored
PCI drivers should use this define to declare their PCI ID table. Reviewed-by:
Tomer Tayar <ttayar@habana.ai> Signed-off-by:
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Dotan Barak authored
Make all the CB handles printed in the same way and not some as decimal and some as hex numbers. Signed-off-by:
Dotan Barak <dbarak@habana.ai> Reviewed-by:
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Oded Gabbay authored
Update the mapping to the latest one used by the Firmware. No impact on the driver in this update. Reviewed-by:
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Adam Aharon authored
Set the STMTCSR.COMPEN bit to enable leading-zero trace data compression functionality for the extended stimulus ports. Signed-off-by:
Adam Aharon <aaharon@habana.ai> Reviewed-by:
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Ofir Bitton authored
Load CPU device boot loader during driver boot time in order to avoid flash write for every boot loader update. To preserve backward-compatibility, skip the device boot load if the device doesn't request it. Signed-off-by:
Ofir Bitton <obitton@habana.ai> Reviewed-by:
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Oded Gabbay authored
The user must leave space for 2xMSG_PROT in the external CB, so adjust the define of max size accordingly. The driver, however, can still create a CB with the maximum size of 2MB. Therefore, we need to add a check specifically for the user requested size. Reviewed-by:
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Christine Gharzuzi authored
Support hwmon_temp_reset_histroy, hwmon_in_reset_history and hwmon_curr_reset attribute which resets the historical highest value. Signed-off-by:
Christine Gharzuzi <cgharzuzi@habana.ai> Reviewed-by:
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Tomer Tayar authored
Align the protection bits configuration of all TPC cores to be as of TPC core 0. Fixes: a513f9a7 ("habanalabs: make tpc registers secured") Signed-off-by:
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Tomer Tayar authored
Allow user access to TPC LFSR register, as it might be accessed by TPC kernels. Signed-off-by:
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Tomer Tayar authored
Add a new opcode to the INFO IOCTL that retrieves the device time alongside the host time, to allow a user application that want to measure device time together with host time (such as a profiler) to synchronize these times. Signed-off-by:
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kbuild test robot authored
set function to be static as it is not called from outside its file. Signed-off-by:
kbuild test robot <lkp@intel.com> Reviewed-by:
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- 17 May, 2020 9 commits
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Oded Gabbay authored
When we have DMA QMAN with multiple streams, we need to know whether the command buffer contains at least one DMA packet in order to configure the barriers correctly when adding the 2xMSG_PROT at the end of the JOB. If there is no DMA packet, then there is no need to put engine barrier. This is relevant only for GAUDI as GOYA doesn't have streams so the engine can't be busy by another stream. Reviewed-by:
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Oded Gabbay authored
Retrieve from the firmware the DMA mask value we need to set according to the device's PCI controller configuration. This is needed when working on POWER9 machines, as the device's PCI controller is configured in a different way in those machines. Reviewed-by:
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Oded Gabbay authored
Add comments for the various errors and states of the firmware during boot. Add a mapping of a new register that will tell the driver whether the firmware executed the request from the driver or if it has encountered an error. Add a new enum for the possible values of this register. Reviewed-by:
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Oded Gabbay authored
When doing training, the DL framework (e.g. tensorflow) performs hundreds of thousands of memory allocations and mappings. In case the driver needs to perform hard-reset during training, the driver kills the application and unmaps all those memory allocations. Unfortunately, because of that large amount of mappings, the driver isn't able to do that in the current timeout (5 seconds). Therefore, increase the timeout significantly to 30 seconds to avoid situation where the driver resets the device with active mappings, which sometime can cause a kernel bug. BTW, it doesn't mean we will spend all the 30 seconds because the reset thread checks every one second if the unmap operation is done. Reviewed-by:
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Oded Gabbay authored
When the system administrator asks the driver to soft or hard reset the device through sysfs, the driver should display a warning in the kernel log to explain why it suddenly resets the device. Reviewed-by:
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Oded Gabbay authored
Move the code of device CPU initialization from being ASIC-Dependent to common code. In addition, add support for the new error reporting feature of the firmware boot code. Reviewed-by:
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Omer Shpigelman authored
We want to remove the following restrictions/assumptions in our driver: 1. The H/W queue index is also the completion queue index. 2. The H/W queue index is also the IRQ number of the completion queue. 3. All queues of the same type have consecutive indexes. Therefore we add the support for H/W queues of the same type with nonconsecutive indexes and completion queue index and IRQ number different than the H/W queue index. Signed-off-by:
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Omer Shpigelman authored
Stop-on-error mode in DMA is useful as it stops the transaction immediately upon error e.g. page fault. But it may cause the next command submission to fail as is leaves the DMA in unstable state. Therefore we remove the stop-on-error configuration from the DMA. Stop-on-err is still available for debug. Signed-off-by:
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Oded Gabbay authored
Upon reset of the ASIC, the driver would have waited for the CPU to come out of reset before finishing the reset process. This was done for the purpose of making the CPU available to answer FLR requests. However, when a VM shuts down, the driver isn't removed so a reset never happens. Therefore, remove this waiting period as we don't need it. Reviewed-by:
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- 15 May, 2020 4 commits
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Akira Shimahara authored
Adding bulk read support: Sending a 'trigger' command in the dedicated sysfs entry of bus master device send a conversion command for all the slaves on the bus. The sysfs entry is added as soon as at least one device supporting this feature is detected on the bus. The behavior of the sysfs reading temperature on the device is as follow: * If no bulk read pending, trigger a conversion on the device, wait for the conversion to be done, read the temperature in device RAM * If a bulk read has been trigger, access directly the device RAM This behavior is the same on the 2 sysfs entries ('temperature' and 'w1_slave'). Reading the therm_bulk_read sysfs give the status of bulk operations: * '-1': conversion in progress on at least 1 sensor * '1': conversion complete but at least one sensor has not been read yet * '0': no bulk operation. Reading temperature on ecah device will trigger a conversion As not all devices support bulk read feature, it has been added in device family structure. The attribute is set at master level as soon as a supporting device is discover. It is removed when the last supported device leave the bus. The count of supported device is kept with the static counter bulk_read_device_counter. A strong pull up is apply on the line if at least one device required it. The duration of the pull up is the max time required by a device on the line, which depends on the resolution settings of each device. The strong pull up could be adjust with the a module parameter. Updating documentation in Documentation/ABI/testing/sysfs-driver-w1_therm and Documentation/w1/slaves/w1_therm.rst accordingly. Signed-off-by:Akira Shimahara <akira215corp@gmail.com> Link: https://lore.kernel.org/r/20200511203820.411483-1-akira215corp@gmail.comSigned-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Akira Shimahara authored
Adding device alarms settings by a dedicated sysfs entry alarms (RW): read or write TH and TL in the device RAM. Checking devices in alarm state could be performed using the master search command. As alarms temperature level are store in a 8 bit register on the device and are signed values, a safe cast shall be performed using the min and max temperature that device are able to measure. This is done by int_to_short inline function. A 'write_data' field is added in the device structure, to bind the correct writing function, as some devices may have 2 or 3 bytes RAM. Updating Documentation/ABI/testing/sysfs-driver-w1_therm accordingly. Signed-off-by:
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Akira Shimahara authored
Optimizing temperature reading by reducing waiting conversion time according to device resolution settings, as per device specification. This is device dependent as not all the devices supports resolution setting, so it has been added in device family structures. The process to read the temperature on the device has been adapted in a new function 'convert_t()', which replace the former 'read_therm()', is introduce to deal with this timing. Strong pull up is also applied during the required time, according to device power status needs and 'strong_pullup' module parameter. 'temperature_from_RAM()' function is introduced to get the correct temperature computation (device dependent) from device RAM data. An new sysfs entry has been added to ouptut only temperature. The old entry w1_slave has been kept for compatibility, without changing its output format. Updating Documentation/ABI/testing/sysfs-driver-w1_therm accordingly. Signed-off-by:
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Akira Shimahara authored
The driver implement 2 hardware functions to access device RAM: * copy_scratchpad * recall_scratchpad They act according to device specifications. As EEPROM operations are not device dependent (all w1_therm can perform EEPROM read/write operation following the same protocol), it is removed from device families structures. Updating Documentation/ABI/testing/sysfs-driver-w1_therm accordingly. Signed-off-by:
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