- 15 Mar, 2023 40 commits
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Krzysztof Kozlowski authored
The SPI controller nodes do not use/allow cs-select property: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected) Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
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Krzysztof Kozlowski authored
The SPI controller nodes do not use/allow label property: apq8096-db820c.dtb: spi@7575000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The SPI controller nodes do not use/allow label property: sdm845-db845c.dtb: spi@888000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The serial node does not use/allow address/size cells: qdu1000-idp.dtb: geniqup@9c0000: serial@99c000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) Fixes: 6bd20c54 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by: -
Krzysztof Kozlowski authored
There is only one output port, thus out-ports should not have 'address/size-cells' and unit addresses. 'reg-names' are also not allowed by bindings. qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+' qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index' property: sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected) Signed-off-by: -
Bartosz Golaszewski authored
There's a typo in the @<address> part of the uart9 label. Fix it. Fixes: 10d900a8 ("arm64: dts: sm8150: add the QUPv3 high-speed UART node") Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Tested-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by:
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Konrad Dybcio authored
Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away. Signed-off-by:
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Mukesh Ojha authored
Add a simple-mfd representing IMEM on SM8450 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Reviewed-by:
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Bartosz Golaszewski authored
Add a node for the cpufreq engine and specify the frequency domains for all CPUs. Signed-off-by:
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Krzysztof Kozlowski authored
Correct indentation. Signed-off-by:
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Krzysztof Kozlowski authored
The WCD9335 audio codec on Slimbus is a property of a board, not SoC, thus it should not be present in MSM8996 DTSI. Keep it in specific boards, so it won't appear incomplete in the boards not having it. Signed-off-by:
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Konrad Dybcio authored
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by:
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Konrad Dybcio authored
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by:
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Konrad Dybcio authored
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by:
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Konrad Dybcio authored
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
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Bartosz Golaszewski authored
This adds basic support for the Qualcomm sa8775p platform and the reference board: sa8775p-ride. The dt files describe the basics of the SoC and enable booting to shell. Signed-off-by:
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Konrad Dybcio authored
Add a PM8998-specific compatible to the coincell charger and keep the PM8941 one as fallback. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Konrad Dybcio authored
The name stm-data-base comes from ancient (msm-3.10 or older) downstream kernels. Upstream uses stm-stimulus-base instead. Fix it. Fixes: 783abfa2 ("arm64: dts: qcom: msm8998: Add Coresight support") Signed-off-by:
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