- 15 Jun, 2024 16 commits
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Dan Carpenter authored
Unlike copy_from_user(), put_user() and get_user() return -EFAULT on error. Use the error code directly instead of setting it. Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/04a018e8-7433-4f67-8ddd-9357a0114f87@moroto.mountainSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski authored
Russell King says: ==================== net: stmmac: provide platform select_pcs method This series adds a select_pcs() method to the stmmac platform data to allow platforms that need to provide their own PCSes to do so, moving the decision making into platform code. This avoids questions such as "what should the priority of XPCS vs some other platform PCS be?" and when we provide a PCS for the internal PCS, how that interacts with both the XPCS and platform provided PCS. Note that if a platform implements the select_pcs() method, then the return values are: - a phylink_pcs pointer - the PCS to be used. - NULL - no phylink_pcs to be used. Otherwise (if not implemented or returns an error-pointer), then allow the the stmmac internal PCS to be used if appropriate (once that patch set is merged.) Patch 1 introduces the new method. Patch 2 converts Intel mGBE to use this to provide the XPCS and removes the XPCS decision making from core code. Patch 3 provides an implementation for rzn1 to return its PCS. Patch 4 does the same for socfpga. Patch 5 removes the core code returning priv->hw->phylink_pcs. No functional change is anticipated. Once this has been merged, it will be expected that platforms should populate all three PCS methods or none of the PCS methods. ==================== Link: https://lore.kernel.org/r/ZmrLbdwv6ALoy+gs@shell.armlinux.org.ukSigned-off-by:
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Russell King (Oracle) authored
Since all platform providers of PCS now populate the select_pcs() method, there is no need for the common code to look at priv->hw->phylink_pcs, so remove it. Reviewed-by:
Romain Gantois <romain.gantois@bootlin.com> Signed-off-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/E1sHhoh-00FetT-3S@rmk-PC.armlinux.org.ukSigned-off-by:
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Russell King (Oracle) authored
Provide a .select_pcs() implementation which returns the phylink PCS that was created in the .pcs_init() method. Reviewed-by:
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Russell King (Oracle) authored
Provide a .select_pcs() implementation which returns the phylink PCS that was created in the .pcs_init() method. Tested-by:
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Russell King (Oracle) authored
Move the code returning the XPCS into dwmac-intel, which is the only user of XPCS. Fill in the select_pcs() implementation only when we are going to setup the XPCS, thus when it should be present. Signed-off-by:
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Russell King (Oracle) authored
Allow platform drivers to provide their logic to select an appropriate PCS. Tested-by:
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Jakub Kicinski authored
Tariq Toukan says: ==================== mlx5 misc patches 2023-06-13 This patchset contains small code cleanups and enhancements from the team to the mlx5 core and Eth drivers. Series generated against: commit 3ec8d757 ("CDC-NCM: add support for Apple's private interface") ==================== Link: https://lore.kernel.org/r/20240613210036.1125203-1-tariqt@nvidia.comSigned-off-by:
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Rahul Rameshbabu authored
Calculate the pseudo-header checksum for both IPSec transport mode and IPSec tunnel mode for mlx5 devices that do not implement a pure hardware checksum offload for L4 checksum calculation. Introduce a capability bit that identifies such mlx5 devices. Signed-off-by:
Rahul Rameshbabu <rrameshbabu@nvidia.com> Reviewed-by:
Gal Pressman <gal@nvidia.com> Reviewed-by:
Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by:
Tariq Toukan <tariqt@nvidia.com> Link: https://lore.kernel.org/r/20240613210036.1125203-7-tariqt@nvidia.comSigned-off-by:
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Gal Pressman authored
Use the tcp specific helpers to calculate the tcp pseudo header checksum instead of the csum_*_magic ones. Signed-off-by:
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Gal Pressman authored
The code no longer treats only UDP tunnels, adjust the outdated comment. Signed-off-by:
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Moshe Shemesh authored
Replace deprecated strcpy with strscpy. Signed-off-by:
Moshe Shemesh <moshe@nvidia.com> Signed-off-by:
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Chris Mi authored
Currently a ct entry is stored in both ct and ct-nat tables. ct action is directed to the ct table, while ct nat action is directed to the nat table. ct-nat entries perform the nat header rewrites, if required. The current design assures that a ct action will match in hardware even if the tuple has nat configured, it will just not execute it. However, storing each connection in two tables increases the system's memory consumption while reducing its insertion rate. Offload a connection to either ct or the ct-nat table. Add a miss fall-through rule from ct-nat table to the ct table allowing ct(nat) action on non-natted connections. ct action on natted connections, by default, will be handled by the software miss path. Signed-off-by:
Paul Blakey <paulb@nvidia.com> Signed-off-by:
Chris Mi <cmi@nvidia.com> Signed-off-by:
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Cosmin Ratiu authored
TSAR is the correct spelling (Transmit Scheduling ARbiter). Signed-off-by:
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Chris Packham authored
The Realtek RTL8224 PHY is a 2.5Gbps capable PHY. It only uses the clause 45 MDIO interface and can leverage the support that has already been added for the other 822x PHYs. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20240611053415.2111723-1-chris.packham@alliedtelesis.co.nzSigned-off-by:
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Jakub Kicinski authored
Commit 12c2d0a5 ("net: lan966x: add ethtool configuration and statistics") added support for various standard stats. We should not clear the stats which are not collected by the device. Core code uses a special initializer to detect when device does not report given stat. Acked-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20240613003222.3327368-1-kuba@kernel.orgSigned-off-by:
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- 14 Jun, 2024 24 commits
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Chris Lew authored
Ignore the ENODEV failures returned by kernel_sendmsg(). These errors indicate that either the local port has been closed or the remote has gone down. Neither of these scenarios are fatal and will eventually be handled through packets that are later queued on the control port. Signed-off-by:
Chris Lew <quic_clew@quicinc.com> Signed-off-by:
Sarannya Sasikumar <quic_sarannya@quicinc.com> Reviewed-by:
Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/20240612063156.1377210-1-quic_sarannya@quicinc.comSigned-off-by:
Paolo Abeni <pabeni@redhat.com>
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Paolo Abeni authored
Christophe Roullier says: ==================== Series to deliver Ethernet for STM32MP13 STM32MP13 is STM32 SOC with 2 GMACs instances GMAC IP version is SNPS 4.20. GMAC IP configure with 1 RX and 1 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek) V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml) Remark from Serge Semin (upate commits msg) V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to manage PHY regulator (in glue or PHY side) - Integrate RFC from Marek - Remark from Rob Herring in YAML documentation V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg) - Remark from Rasmus (add sign-off, add base-commit) - Remark from Sai Krishna Gajula V5: - Fix warning during build CHECK_DTBS - Remark from Marek (glue + DT update) - Remark from Krzysztof about YAML (Make it symmetric) V6: - Replace pr_debug by dev_dbg - Split serie driver/DTs separately V7: - Remark from Marek (update sysconfig register mask) ==================== Link: https://lore.kernel.org/r/20240611083606.733453-1-christophe.roullier@foss.st.comSigned-off-by: -
Christophe Roullier authored
Add Ethernet support for STM32MP13. STM32MP13 is STM32 SOC with 2 GMACs instances. GMAC IP version is SNPS 4.20. GMAC IP configure with 1 RX and 1 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Signed-off-by:
Christophe Roullier <christophe.roullier@foss.st.com> Reviewed-by:
Marek Vasut <marex@denx.de> Signed-off-by:
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Christophe Roullier authored
Add possibility to have second argument in syscon property to manage mask. This mask will be used to address right BITFIELDS of PMCR register. Signed-off-by:
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Marek Vasut authored
Trivial, fix up the comments using 'Mhz' to 'MHz'. No functional change. Signed-off-by:
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Marek Vasut authored
Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of pr_debug() and hand-written PHY mode decoding. This way, each debug print has associated device with it and duplicated mode decoding is removed. Signed-off-by:
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Marek Vasut authored
Pull the PMCR clock mux configuration into a separate function. This is the final change of three, which moves external clock rate validation, external clock selector decoding, and clock mux configuration into separate functions. This should make the code easier to understand. No functional change intended. Signed-off-by:
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Marek Vasut authored
Pull the external clock selector into a separate function, to avoid conflating it with external clock rate validation and clock mux register configuration. This should make the code easier to read and understand. The dwmac->enable_eth_ck variable in the end indicates whether the MAC clock are supplied by external oscillator (true) or internal RCC clock IP (false). The dwmac->enable_eth_ck value is set based on multiple DT properties, some of them deprecated, some of them specific to bus mode. The following DT properties and variables are taken into account. In each case, if the property is present or true, MAC clock is supplied by external oscillator. - "st,ext-phyclk", assigned to variable dwmac->ext_phyclk - Used in any mode (MII/RMII/GMII/RGMII) - The only non-deprecated DT property of the three - "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg - Valid only in GMII/RGMII mode - Deprecated property, backward compatibility only - "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg - Valid only in RMII mode - Deprecated property, backward compatibility only The stm32mp1_select_ethck_external() function handles the aforementioned DT properties and sets dwmac->enable_eth_ck accordingly. The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external() first and then only use dwmac->enable_eth_ck to determine hardware clock mux settings. No functional change intended. Signed-off-by:
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Marek Vasut authored
Pull the external clock frequency validation into a separate function, to avoid conflating it with external clock DT property decoding and clock mux register configuration. This should make the code easier to read and understand. This does change the code behavior slightly. The clock mux PMCR register setting now depends solely on the DT properties which configure the clock mux between external clock and internal RCC generated clock. The mux PMCR register settings no longer depend on the supplied clock frequency, that supplied clock frequency is now only validated, and if the clock frequency is invalid for a mode, it is rejected. Previously, the code would switch the PMCR register clock mux to internal RCC generated clock if external clock couldn't provide suitable frequency, without checking whether the RCC generated clock frequency is correct. Such behavior is risky at best, user should have configured their clock correctly in the first place, so this behavior is removed here. Signed-off-by:
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Christophe Roullier authored
New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Lukasz Majewski authored
This patch provides support for sending supervision HSR frames with MAC addresses stored in ProxyNodeTable when RedBox (i.e. HSR-SAN) is enabled. Supervision frames with RedBox MAC address (appended as second TLV) are only send for ProxyNodeTable nodes. This patch series shall be tested with hsr_redbox.sh script. Signed-off-by:
Lukasz Majewski <lukma@denx.de> Reviewed-by:
Wojciech Drewek <wojciech.drewek@intel.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Jakub Kicinski authored
Martin Schiller says: ==================== net: dsa: lantiq_gswip: code improvements This patchset for the lantiq_gswip driver is a collection of minor fixes and coding improvements by Martin Blumenstingl without any real changes in the actual functionality. ==================== Link: https://lore.kernel.org/r/20240611135434.3180973-1-ms@dev.tdt.deSigned-off-by:
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Martin Blumenstingl authored
Print that no FID is found for bridge %s instead of the incorrect message that the port is not part of a bridge. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
Martin Schiller <ms@dev.tdt.de> Link: https://lore.kernel.org/r/20240611135434.3180973-13-ms@dev.tdt.deSigned-off-by:
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Martin Blumenstingl authored
Update the comments in gswip_port_vlan_filtering() so it's clear that there are two separate cases, one for "tag based VLAN" and another one for "port based VLAN". Suggested-by:
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Martin Schiller authored
The port validation in gswip_add_single_port_br() is superfluous and can be omitted. Suggested-by:
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Martin Blumenstingl authored
Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Also, for dynamic (learned) entries, bits [7:4] in mac_bridge.val[0] represents the port. Introduce new macros GSWIP_TABLE_MAC_BRIDGE_KEY3_FID and GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT macro and use it throughout the driver. Also rename and update GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC to use the BIT() macro. This makes the driver code easier to understand. Signed-off-by:
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Martin Blumenstingl authored
The addr variable in gswip_port_fdb_dump() stores a mac address. Use ETH_ALEN to make this consistent across other drivers. Signed-off-by:
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Martin Blumenstingl authored
Make the check for the CPU port in gswip_port_change_mtu() consistent with other areas of the driver by using dsa_is_cpu_port(). Signed-off-by:
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Martin Schiller authored
Before commit 74be4bab ("net: dsa: do not enable or disable non user ports"), gswip_port_enable/disable() were also executed for the cpu port in gswip_setup() which disabled the cpu port during initialization. Let's restore this by removing the dsa_is_user_port checks. Also, let's clean up the gswip_port_enable() function so that we only have to check for the cpu port once. The operation reordering done here is safe. Signed-off-by:
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Martin Blumenstingl authored
We don't need to manually call gswip_port_enable() from within gswip_setup() for the CPU port. DSA does this automatically for us. Signed-off-by:
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Martin Blumenstingl authored
dev_err_probe() can be used to simplify the existing code. Also it means we get rid of the following warning which is seen whenever the PMAC (Ethernet controller which connects to GSWIP's CPU port) has not been probed yet: gswip 1e108000.switch: dsa switch register failed: -517 Signed-off-by:
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Martin Schiller authored
Some dev_err are missing the terminating \n. Let's add that. Suggested-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
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Martin Blumenstingl authored
Add the CPU port to gswip_xrx200_phylink_get_caps() and gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus, so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL. Signed-off-by:
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Martin Schiller authored
Convert the lantiq,gswip bindings to YAML format. Also add this new file to the MAINTAINERS file. Furthermore, the CPU port has to specify a phy-mode and either a phy or a fixed-link. Since GSWIP is connected using a SoC internal protocol there's no PHY involved. Add phy-mode = "internal" and a fixed-link to the example code to describe the communication between the PMAC (Ethernet controller) and GSWIP switch. Signed-off-by:
Rob Herring (Arm) <robh@kernel.org> Reviewed-by:
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