- 06 Apr, 2018 5 commits
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Stephen Boyd authored
Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next * clk-mediatek: clk: mediatek: add audsys support for MT2701 clk: mediatek: add devm_of_platform_populate() for MT7622 audsys dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 * clk-hisi: clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() clk: hisilicon: mark wdt_mux_p[] as const clk: hisilicon: Mark phase_ops static clk: hi3798cv200: add emmc sample and drive clock clk: hisilicon: add hisi phase clock support clk: hi3798cv200: add COMBPHY0 clock support clk: hi3798cv200: fix define indentation clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK clk: hi3798cv200: correct IR clock parent clk: hi3798cv200: fix unregister call sequence in error path * clk-allwinner: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name * clk-ux500: clk: ux500: Drop AB8540/9540 support * clk-renesas: (27 commits) clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: fix false-positive Wmaybe-uninitialized warning clk: renesas: r8a77965: Replace DU2 clock clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock ...
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Stephen Boyd authored
Merge branches 'clk-mvebu', 'clk-phase', 'clk-nxp', 'clk-mtk2712' and 'clk-qcom-rpmcc' into clk-next * clk-mvebu: clk: mvebu: armada-38x: add support for missing clocks clk: mvebu: cp110: Fix clock tree representation * clk-phase: clk: Don't show the incorrect clock phase clk: update cached phase to respect the fact when setting phase * clk-nxp: clk: lpc32xx: Set name of regmap_config * clk-mtk2712: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clocks for MT2712 * clk-qcom-rpmcc: clk: qcom: rpmcc: Add support to XO buffered clocks
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Stephen Boyd authored
Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' and 'clk-gpio' into clk-next * clk-spreadtrum: clk: sprd: add RTC gate for SC9860 dt-bindings: clocks: add APB RTC gate for SC9860 * clk-stm32f: clk: stm32: Add clk entry for SDMMC2 on stm32F769 clk: stm32: Add DSI clock for STM32F469 Board clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK * clk-stm32mp1: clk: stm32: add configuration flags for each of the stm32 drivers clk: stm32mp1: add Debug clocks clk: stm32mp1: add MCO clocks clk: stm32mp1: add RTC clock clk: stm32mp1: add Peripheral & Kernel Clocks clk: stm32mp1: add Kernel timers clk: stm32mp1: add Sub System clocks clk: stm32mp1: add Post-dividers for PLL clk: stm32mp1: add PLL clocks clk: stm32mp1: add Source Clocks for PLLs clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators clk: stm32mp1: Introduce STM32MP1 clock driver dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings * clk-hi655x: clk: enable hi655x common clk automatically * clk-gpio: clk: clk-gpio: Allow GPIO to sleep in set/get_parent
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Stephen Boyd authored
Merge branches 'clk-versatile', 'clk-doc', 'clk-must-check', 'clk-qcom' and 'clk-debugfs' into clk-next * clk-versatile: clk: versatile: Remove WARNs in ->round_rate() clk: versatile: add min/max rate boundaries for vexpress osc clock * clk-doc: Documentation: clk: enable lock is not held for clk_is_enabled API * clk-must-check: clk: add more __must_check for bulk APIs * clk-qcom: clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider() clk: qcom: gcc-msm8996: Mark aggre0 noc clks as critical * clk-debugfs: clk: Re-use DEFINE_SHOW_ATTRIBUTE() macro
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Stephen Boyd authored
* clk-ti: clk: keystone: sci-clk: add support for dynamically probing clocks clk: ti: add support for clock latching to mux clocks clk: ti: add support for clock latching to divider clocks clk: ti: add generic support for clock latching clk: ti: add support for register read-modify-write low-level operation dt-bindings: clock: ti: add latching support to mux and divider clocks * clk-amlogic: (50 commits) clk: meson: Drop unused local variable and add static clk: meson: clean-up clk81 clocks clk: meson: add fdiv clock gates clk: meson: add mpll pre-divider clk: meson: axg: add hifi pll clock clk: meson: axg: add hifi clock bindings clk: meson: add ROUND_CLOSEST to the pll driver clk: meson: add gp0 frac parameter for axg and gxl clk: meson: improve pll driver results with frac clk: meson: remove special gp0 lock loop clk: meson: poke pll CNTL last clk: meson: add fractional part of meson8b fixed_pll clk: meson: use hhi syscon if available clk: meson: remove obsolete cpu_clk clk: meson: rework meson8b cpu clock clk: meson: split divider and gate part of mpll clk: meson: migrate plls clocks to clk_regmap clk: meson: migrate the audio divider clock to clk_regmap clk: meson: migrate mplls clocks to clk_regmap clk: meson: add regmap helpers for parm ... * clk-tegra: clk: tegra: Fix pll_u rate configuration clk: tegra: Specify VDE clock rate clk: tegra20: Correct PLL_C_OUT1 setup clk: tegra: Mark HCLK, SCLK and EMC as critical clk: tegra: MBIST work around for Tegra210 clk: tegra: add fence_delay for clock registers clk: tegra: Add la clock for Tegra210 * clk-samsung: (22 commits) clk: samsung: Mark a few things static clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412 clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices clk: samsung: exynos5420: Add more entries to EPLL rate table clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU clk: samsung: Add Exynos5 sub-CMU clock driver soc: samsung: pm_domains: Add blacklisting clock handling clk: samsung: Add compile time PLL rate validators clk: samsung: s3c2410: Fix PLL rates clk: samsung: exynos7: Fix PLL rates clk: samsung: exynos5433: Fix PLL rates clk: samsung: exynos5260: Fix PLL rates clk: samsung: exynos5250: Fix PLL rates clk: samsung: exynos3250: Fix PLL rates clk: exynos5433: Extend list of available AUD_PLL output frequencies clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclk clk: samsung: Add a git tree entry to MAINTAINERS clk: samsung: Remove redundant dev_err call in exynos_audss_clk_probe() ...
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- 23 Mar, 2018 3 commits
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Fix the incorrect display clock on R-Car M3-N, - Always use readl()/writel(), - Small fixes. * tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: renesas: r8a77965: Replace DU2 clock
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Linus Walleij authored
The AB8540 was an evolved version of the AB8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the AB8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes from Maxime Ripard: Our usual bunch of changes for the next merge window. The most significant addition is the support of the H6 clock unit. Other than that, there's a bunch of fixes for the video clocks on the H3 and H5, and some Kconfig cleanup. * tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name
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- 21 Mar, 2018 10 commits
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Magnus Damm authored
Adjust the R8A77980-specific #ifdefs to use CLK instead of ARCH to follow same style as other SoCs. Fixes: ce15783c ("clk: renesas: cpg-mssr: add R8A77980 support") Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Cfr. commit 30ad3cf0 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()"). Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Geert Uytterhoeven authored
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Geert Uytterhoeven authored
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Geert Uytterhoeven authored
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Geert Uytterhoeven authored
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Geert Uytterhoeven authored
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Geert Uytterhoeven authored
On arm32/arm64, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by:
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Icenowy Zheng authored
The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by:Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com>
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- 20 Mar, 2018 3 commits
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Wei Yongjun authored
platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Fixes: 32226916 ("clk: hisilicon: add hisi_clk_alloc function.") Signed-off-by:
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Ryder Lee authored
Add clock driver support for MT2701 audsys. Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Signed-off-by:
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Ryder Lee authored
Add devm_of_platform_populate() to populate devices which are children of the root node. Signed-off-by:
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- 19 Mar, 2018 19 commits
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Srinivas Kandagatla authored
XO is onchip buffer clock to generate 19.2MHz. This patch adds support to 5 XO buffer clocks found on PMIC8921, these buffer clocks can be controlled from external pin or in manual mode. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Weiyi Lu authored
According to ECO design change, 1. add new clock mux data and change some 2. add new clock gate data and clock factor data 3. change status register offset of infra subsystem Signed-off-by:
Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by:
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Weiyi Lu authored
add new clocks according to ECO design change Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Jeffy Chen authored
We are now allowing to register debugfs without a valid device, and not having a valid name will end up using "dummy*" to create debugfs dir. Signed-off-by:
Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
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Shawn Lin authored
It's found that the clock phase output from clk_summary is wrong compared to the actual phase reading from the register. cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample sdio_sample 0 1 0 50000000 0 -22 It exposes an issue that clk core, clk_core_get_phase, always returns the cached core->phase which should be either updated by calling clk_set_phase or directly from the first place the clk was registered. When registering the clk, the core->phase geting from ->get_phase() may return negative value indicating error. This is quite common since the clk's phase may be highly related to its parent chain, but it was temporarily orphan when registered, since its parent chains hadn't be ready at that time, so the clk drivers decide to return error in this case. However, if no clk_set_phase is called or maybe the ->set_phase() isn't even implemented, the core->phase would never be updated. This is wrong, and we should try to update it when all its parent chains are settled down, like the way of updating clock rate for that. But it's not deserved to complicate the code now and just update it anyway when calling clk_core_get_phase, which would be much simple and enough. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Acked-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Richard Genoud authored
Clearfog boards can come with a CPU clocked at 1600MHz (commercial) or 1333MHz (industrial). They have also some dip-switches to select a different clock (666, 800, 1066, 1200). The funny thing is that the recovery button is on the MPP34 fq selector. So, when booting an industrial board with this button down, the frequency 666MHz is selected (and the kernel didn't boot). This patch add all the missing clocks. The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ). Fixes: 0e85aece ("clk: mvebu: add clock support for Armada 380/385") Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f5: clk: mvebu: armada-38x: add support for 1866MHz variants Cc: <stable@vger.kernel.org> # 3.16.x Signed-off-by:
Richard Genoud <richard.genoud@gmail.com> Acked-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
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Mike Looijmans authored
When changing or retrieving clock parents, the caller is in a sleepable state (like prepare) so the GPIO operation need not be atomic. Replace gpiod_{g|s}et_value with gpiod_{g|s}et_value_cansleep in the {g|s}et_parent calls for the GPIO based clock mux. This fixes a "slowpath" warning when the GPIO controller is an I2C expander or something similar. Signed-off-by:Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by:
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Riku Voipio authored
Without COMMON_CLK_HI655X Wifi and bluetooth are non-functional on Hikey. As suggested by Arnd, enable the driver automatically when the parent driver is selected. With sensible defaults in place, we can leave other choices for EXPERT. Cc: John Stultz <john.stultz@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Suggested-by:
Arnd Bergmann <arnd@linaro.org> Signed-off-by:
Riku Voipio <riku.voipio@linaro.org> Reviewed-by:
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Benjamin Gaignard authored
Add two configuration flags to be able to not compile all the time stm32f and stm32h7 drivers when ARCH_STM32 is set. That help to save some space on those small platforms. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
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Patrice Chotard authored
STM32F769 has 2 SDMMC port, add clock entry for the second one. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Gabriel Fernandez authored
This patch adds DSI clock for STM32F469 board Signed-off-by:
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Gabriel Fernandez authored
Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK hsi and sysclk are overwritten by gpioa and gpiob. Signed-off-by:
Philippe Cornu <philippe.cornu@st.com> Reviewed-by:
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Ryder Lee authored
This patch adds a compatible string for MT2701. Signed-off-by:
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Ryder Lee authored
The MediaTek audio hardware block that exposes functionalities that are handled by separate subsystems in the kernel. These functions are all mapped somewhere at 0x112xxxxx, and there are some control bits are mixed up with other functions within the same registers. This patch modifies example to illustrate child nodes. Signed-off-by:
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Ryder Lee authored
Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Sean Wang authored
The clock for which all PWM devices on MT7623 or MT2701 actually depending on has to be divided by four from its parent clock axi_sel in the clock path prior to PWM devices. Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of clock axi_sel allows that PWM devices can have the correct resolution calculation. Cc: stable@vger.kernel.org Fixes: e9862118 ("clk: mediatek: Add MT2701 clock support") Signed-off-by:
Sean Wang <sean.wang@mediatek.com> Signed-off-by:
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Sean Wang authored
Just add binding for a fixed-factor clock axisel_d4, which would be referenced by PWM devices on MT7623 or MT2701 SoC. Cc: stable@vger.kernel.org Fixes: 1de9b216 ("clk: mediatek: Add dt-bindings for MT2701 clocks") Signed-off-by:
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Gregory CLEMENT authored
Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by:
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Andy Shevchenko authored
...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
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